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ARTERY AT32F435 Series, Reference Manual

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ARTERY AT32F435 Series Reference Manual Download Page 646

  AT32F435/437

 

Series  Reference  Manual

 

2022.11.11

 

Page 646 

 

Rev 2.03

 

packs two captured data into a word data. The word data is made up of two half words. The first captured 
data is placed in the 12 least significant bits of the least significant half word, and the last captured data 
is placed in the 12 least significant bits of the most significant half word, and the remaining are cleared 
to zero. 

14-bit parallel data (PDL=3) 

When the PDL bit is programmed to 3, the DVP captures a 14-bit data every DVP_PCLK clock, and 
packs two captured data into a word data. The word data is made up of two half words. The first captured 
data is placed in the 14 least significant bits of the least significant half word, and the last captured data 
is placed in the 14 least significant bits of the most significant half word, and the remaining are cleared 
to zero. 
Figure 27-8 PDL configuration and data output packing 

15

8 7

0

31

24 23

16

D0

D1

D2

D3

8-bit (PDL=0)

15

10 9

0

31

26 25

16

D0

6'b0

D1

6'b0

10-bit (PDL=1)

15

12 11

0

31

28 27

16

D0

4'b0

D1

4'b0

12-bit (PDL=2)

1514

13

0

3130

29

16

D0

2'b0

D1

2'b0

14-bit (PDL=3)

 

27.5 Interrupts and interrupt control 

There  are  four  registers  available  to  control  the  interrupts  of  the  DVP  interface.  The  read-only 
DVP_ESTS register is used to describe the synchronization status of error events occurred over the 
course of sampling. The DVP_IENA is used to control interrupt signals, and it can be programmed to 
enable the synchronization status or error interrupts of the corresponding bits, and send them to CPU. 
The interrupts, after enabled, are stored in the read-only DVP_ISTS register, which is used to check the 
event sources. The status in the DVP_ESTS and DVP_ISTS can be cleared by setting the corresponding 
bit in the DVP_ICLR register. The DVP_ICLR is a write-only register and does not need to be cleared. 
DVP supports three synchronization status interrupts: 

Capture frame done 

When the CFDES and CFDIS bits are set (CAP enabled), it indicates the completion of the current frame 
capture. Based on the synchronization logic, the frame capture completed interrupt occurs when the 
frame end signal is detected. If the Crop feature is enabled, the frame capture completed interrupt occurs 
before the end of the crop window. If the Crop feature is not enabled, both CFDES and CFDIS bits have 
no effect. 

Vertical synchronization 

The  VSES  and  VSIS  bits  indicate  that  vertical  synchronization  has  been  obtained.  Vertical 
synchronization  can  be  defined  as  the  start  or  end  of  a  frame,  depending  on  the  VSEID  bit  in  the 
DVP_ACTRL register. 

Horizontal synchronization 

The HSES and HSIS bits indicate that horizontal synchronization has been obtained. The horizontal 
synchronization  can  be  defined  as  the  start  or  end  of  a  line,  depending  on  the  HSEID  bit  in  the 
DVP_ACTRL register. 
The DVP supports two types of error interrupts: 

Output data FIFO overrun 

The OVRES and OVRIS bits (CAP enabled) indicate the error status of output data FIFO overrun. If 

Summary of Contents for AT32F435 Series

Page 1: ...nsor VTS internal reference voltage VINTR VBAT battery voltage monitor VBAT 4 2 x 12 bit D A converters DMA 2 x general purpose DMAs and 1 x EDMA 22 channels in all Up to 116 Fast I O Interfaces All mappable to 16 external interrupt vectors Almost 5 V tolerant Up to 18 Timers TMR Up to 13 x 16 bit timers 2 x 32 bit timers each with 4 IC OC PWM or pulse counter channels 2 x Watchdog timers WDT and ...

Page 2: ...n 55 1 3 1 Flash memory size register 55 1 3 2 Device electronic signature 55 2 Memory resources 56 2 1 Internal memory address map 56 2 2 Flash memory 56 2 3 SRAM memory 59 2 4 Peripheral address map 59 3 Power control PWC 62 3 1 Introduction 62 3 2 Main Features 62 3 3 POR LVR 62 3 4 Power voltage monitor PVM 63 3 5 Power domain 63 3 6 Power saving modes 64 3 7 PWC registers 66 3 7 1 Power contr...

Page 3: ...peripheral reset register2 CRM_APBRST2 79 4 3 7 APB peripheral reset register3 CRM_APBRST3 79 4 3 8 APB1 peripheral reset register CRM_APB1RST 79 4 3 9 APB2 peripheral reset register CRM_APB2RST 81 4 3 10 APB peripheral clock enable register1 CRM_AHBEN1 82 4 3 11 APB peripheral clock enable register2 CRM_AHBEN2 83 4 3 12 APB1 peripheral clock enable register3 CRM_AHBEN3 83 4 3 13 APB1 peripheral c...

Page 4: ...5 3 2 Erase operation 104 5 3 3 Programming operation 105 5 3 4 Read operation 106 5 4 Flash memory protection 106 5 4 1 Access protection 106 5 4 2 Erase program protection 106 5 5 Special functions 106 5 5 1 Security library settings 106 5 6 Flash memory registers 107 5 6 1 Flash performance select register FLASH_PSR 108 5 6 2 Flash unlock register FLASH_UNLOCK 109 5 6 3 Flash user system data u...

Page 5: ...gister0 SLIB_SET_RANGE0 114 5 6 23 Security library address setting register1 SLIB_SET_RANGE1 114 5 6 24 Security library unlock register SLIB_UNLOCK 115 5 6 25 Flash CRC calibration control register FLASH_CRC_CTRL 115 5 6 26 Flash CRC check result register FLASH_CRC_CHKR 115 6 GPIOs and IOMUX 116 6 1 Introduction 116 6 2 Function overview 116 6 2 1 GPIO structure 116 6 2 2 GPIO reset status 116 6...

Page 6: ...iguration register1 SCFG_CFG1 138 7 2 2 SCFG configuration register2 SCFG_CFG2 139 7 2 3 SCFG external interrupt configuration register1 SCFG_ EXINTC1 139 7 2 4 SCFG external interrupt configuration register2 SCFG_ EXINTC2 140 7 2 5 SCFG external interrupt configuration register3 SCFG_ EXINTC3 141 7 2 6 SCFG external interrupt configuration register4 SCFG_ EXINTC4 142 7 2 7 SCFG ultra high sourcin...

Page 7: ... 9 5 5 DMA channel x peripheral address register DMA_CxPADDR x 1 7 162 9 5 6 DMA channel x memory address register DMA_CxMADDR x 1 7 162 9 5 7 DMAMUX selection register DMA_MUXSEL 162 9 5 8 DMAMUX channel x control register DMA_MUXCxCTRL x 1 7 162 9 5 9 DMAMUX generator x control register DMA_MUXGxCTRL x 1 4 163 9 5 10 DMAMUX channel synchronization status register DMA_MUXSYNCSTS 164 9 5 11 DMAMUX...

Page 8: ... management 192 11 5 I2C interrupt requests 194 11 6 I2C debug mode 194 11 7 I2C registers 194 11 7 1 Control register1 I2C_CTRL1 195 11 7 2 Control register2 I2C_CTRL2 196 11 7 3 Address register1 I2C_OADDR1 197 11 7 4 Own address register2 I2C_OADDR2 197 11 7 5 Timing register I2C_CLKCTRL 197 11 7 6 Timeout register I2C_TIMEOUT 197 11 7 7 Status register I2C_STS 198 11 7 8 Status clear register ...

Page 9: ...roduction 211 12 8 2 Receiver configuration 211 12 8 3 Start bit and noise detection 212 12 9 Tx Rx swap 213 12 10Interrupt requests 214 12 11I O pin control 215 12 12USART registers 215 12 12 1 Status register USART_STS 215 12 12 2 Data register USART_DT 216 12 12 3 Baud rate register USART_BAUDR 217 12 12 4 Control register1 USART_CTRL1 217 12 12 5 Control register2 USART_CTRL2 218 12 12 6 Contr...

Page 10: ...235 13 3 5 I2S_CLK controller 236 13 3 6 DMA transfer 238 13 3 7 Transmitter Receiver 238 13 3 8 I2S communication timings 239 13 3 9 Interrupts 240 13 3 10 IO pin control 240 13 4 SPI registers 241 13 4 1 SPI control register1 SPI_CTRL1 Not used in I2 S mode 241 13 4 2 SPI control register2 SPI_CTRL2 242 13 4 3 SPI status register SPI_STS 243 13 4 4 SPI data register SPI_DT 244 13 4 5 SPICRC regi...

Page 11: ...2 to TMR5 252 14 2 1 TMR2 to TMR5 introduction 252 14 2 2 TMR2 to TMR5 main features 252 14 2 3 TMR2 to TMR5 functional overview 252 14 2 3 1 Count clock 252 14 2 3 2 Counting mode 256 14 2 3 3 TMR input function 259 14 2 3 4 TMR output function 261 14 2 3 5 TMR synchronization 264 14 2 3 6 Debug mode 267 14 2 4 TMRx registers 267 14 2 4 1 TMR2 to TMR5 control register1 TMRx_CTRL1 268 14 2 4 2 TMR...

Page 12: ... 3 2 Counting mode 282 14 3 3 3 TMR input function 283 14 3 3 4 TMR output function 286 14 3 3 5 TMR synchronization 288 14 3 3 6 Debug mode 289 14 3 4 TMR9 and TMR12 registers 289 14 3 4 1 TMR9 and TMR12 control register1 TMRx_CTRL1 289 14 3 4 2 TMR9 and TMR12 Slave timer control register TMRx_STCTRL 290 14 3 4 3 TMR9 and TMR12 DMA interrupt enable register TMRx_IDEN 290 14 3 4 4 TMR9 and TMR12 i...

Page 13: ...MR1 and TMR8 functional overview 300 14 4 3 1 Count clock 300 14 4 3 2 Counting mode 304 14 4 3 3 TMR input function 308 14 4 3 4 TMR output function 310 14 4 3 5 TMR brake function 314 14 4 3 6 TMR synchronization 316 14 4 3 7 Debug mode 317 14 4 4 TMR1 TMR8 and TM20 registers 318 14 4 4 1 TMR1 TMR8 and TMR20 control register1 TMRx_CTRL1 318 14 4 4 2 TMR1 TMR8 and TMR20 control register2 TMRx_CTR...

Page 14: ... DMA data register TMRx_DMADT 331 14 4 4 21 TMR1 TMR8 and TMR20 channel mode register3 TMRx_ CM3 331 14 4 4 22 TMR1 TMR8 and TMR20 channel 5 data register TMRx_C5DT 331 15 Window watchdog timer WWDT 332 15 1 WWDT introduction 332 15 2 WWDT main features 332 15 3 WWDT functional overview 332 15 4 Debug mode 333 15 5 WWDT registers 333 15 5 1 Control register WWDT_CTRL 333 15 5 2 Configuration regis...

Page 15: ...ter ERTC_DIV 349 17 4 6 ERTC wakeup timer register ERTC_WAT 349 17 4 7 ERTC coarse calibration register ERTC_CCAL 349 17 4 8 ERTC alarm clock A register ERTC_ALA 350 17 4 9 ERTC alarm clock B register ERTC_ALB 350 17 4 10 ERTC write protection register ERTC_WP 351 17 4 11 ERTC subsecond register ERTC_SBS 351 17 4 12 ERTC time adjustment register ERTC_TADJ 351 17 4 13 ERTC time stamp time register ...

Page 16: ... group conversion mode 361 18 4 3 3 Repetition mode 361 18 4 3 4 Partition mode 362 18 4 4 End of conversion 362 18 4 5 Oversampling 363 18 4 5 1 Oversampling of ordinary group of channels 364 18 4 5 2 Oversampling of preempted group of channels 365 18 4 6 Data management 365 18 4 6 1 Data alignment 365 18 4 6 2 Data read 366 18 4 7 Voltage monitoring 366 18 4 7 1 Status flag and interrupts 367 18...

Page 17: ...er ADC_CSTS 383 18 6 18 ADC common control register ADC_CSTS 385 18 6 19 ADC common data register ADC_CODT 387 19 Digital to analog converter DAC 388 19 1 DAC introduction 388 19 2 DAC main features 388 19 3 Design tips 388 19 4 Functional overview 389 19 4 1 Trigger events 389 19 4 2 Noise Triangular wave generation 389 19 4 3 DAC data alignment 390 19 5 DAC registers 391 19 5 1 DAC control regis...

Page 18: ...ansmission 403 20 6 6 Message reception 405 20 6 7 Error management 405 20 7 CAN registers 406 20 7 1 CAN control and status registers 407 20 7 1 1 CAN master control register CAN_MCTRL 407 20 7 1 2 CAN master status register CAN_MSTS 408 20 7 1 3 CAN transmit status register CAN_TSTS 409 20 7 1 4 CAN receive FIFO 0 register CAN_RF0 412 20 7 1 5 CAN receive FIFO 1 register CAN_RF1 412 20 7 1 6 CAN...

Page 19: ...it register CAN_ FiFBx i 0 13 x 1 2 419 21 Universal serial bus full seed device interface OTGFS 420 21 1 USBFS structure 420 21 2 OTGFS functional description 420 21 3 OTGFS clock and pin configuration 421 21 3 1 OTGFS clock configuration 421 21 3 2 OTGFS pin configuration 421 21 4 OTGFS interrupts 422 21 5 OTGFS functional description 422 21 5 1 OTGFS initialization 422 21 5 2 OTGFS FIFO configu...

Page 20: ...trol IN data transfers 448 21 5 4 15 Non synchronous OUT data transfers 449 21 5 4 16 Synchronous OUT data transfers 451 21 5 4 17 Enable synchronous endpoints 452 21 5 4 18 Incomplete synchronous OUT data transfers 454 21 5 4 19 Incomplete synchronous IN data transfers 455 21 5 4 20 Periodic IN interrupt and synchronous data transfers 455 21 6 OTGFS control and status registers 457 21 6 1 CSR reg...

Page 21: ...FS_HPTXSTS 475 21 6 4 5 OTGFS host all channels interrupt register OTGFS_HAINT 475 21 6 4 6 OTGFS host all channels interrupt mask register OTGFS_HAINTMSK 475 21 6 4 7 OTGFS host port control and status register OTGFS_HPRT 476 21 6 4 8 OTGFS host channelx characteristics register OTGFS_HCCHARx x 0 15 where x channel number 477 21 6 4 9 OTGFS host channelx interrupt register OTGFS_HCINTx x 0 15 whe...

Page 22: ...er OTGFS_DOEPINTx x 0 7 where x if endpoint number 491 21 6 5 15 OTGFS device IN endpoint 0 transfer size register OTGFS_DIEPTSIZ0 492 21 6 5 16 OTGFS device OUT endpoint 0 transfer size register OTGFS_DOEPTSIZ0 492 21 6 5 17 OTGFS device IN endpoint x transfer size register OTGFS_DIEPTSIZx x 1 7 where x is endpoint number 493 21 6 5 18 OTGFS device IN endpoint transmit FIFO status register OTGFS_...

Page 23: ...0 24 4 2 2 Read write operation with different timings 513 24 4 2 3 Multiplexed mode 521 24 4 2 4 Synchronous mode 523 24 4 3 NAND 525 24 4 4 Operating mode 525 24 4 5 Access timings 526 24 4 6 ECC computation 527 24 5 PC card 527 24 5 1 Operating mode 527 24 5 2 Access timings 528 24 6 SDRAM card 529 24 6 1 SDRAM access management 529 24 6 2 Self refresh mode and Power down mode 532 24 7 XMC regi...

Page 24: ...tribute memory timing register 4 XMC_ BK4TMGAT 541 24 7 3 5 IO space timing register 4 XMC_ BK4TMGIO 542 24 7 4 SDRAM controller registers 542 24 7 4 1 SDRAM control register 1 2 SDRAM_CTRL1 SDRAM_CTRL2 542 24 7 4 2 SDRAM timing register 1 2 SDRAM_TM1 SDRAM_TM2 543 24 7 4 3 SDRAM command register SDRAM_CMD 545 24 7 4 4 SDRAM refresh timer register SDRAM_RCNT 545 24 7 4 5 SDRAM status register SDRA...

Page 25: ...O_INTCLR 573 25 4 13 SDIO interrupt mask register SDIO_INTEN 573 25 4 14 SDIOBUF counter register SDIO_BUFCNTR 575 25 4 15 SDIO data BUF register SDIO_BUF 575 26 Ethernet media access control EMAC 576 26 1 EMAC introduction 576 26 1 1 EMAC structure 576 26 1 2 EMAC main features 576 26 2 EMAC functional description 577 26 2 1 EMAC communication interfaces 577 26 2 2 EMAC frame communication 583 26...

Page 26: ... MAC address 3 high register EMAC_MACA3H 620 26 3 20 Ethernet MAC address 3 low register EMAC_MACA3L 621 26 3 21 Ethernet DMA bus mode register EMAC_DMABM 621 26 3 22 Ethernet DMA transmit poll demand register EMAC_DMATPD 623 26 3 23 Ethernet DMA receive poll demand register EMAC_DMARPD 623 26 3 24 Ethernet DMA receive descriptor list address register EMAC_DMARDLADDR 623 26 3 25 Ethernet DMA trans...

Page 27: ... counter register EMAC_MMCRGUFCNT 634 26 3 45 Ethernet PTP time stamp control register EMAC_PTPTSCTRL 634 26 3 46 Ethernet PTP subsecond increment register EMAC_PTPSSINC 636 26 3 47 Ethernet PTP time stamp high register EMAC_PTPTSH 636 26 3 48 Ethernet PTP time stamp low register EMAC_PTPTSL 637 26 3 49 Ethernet PTP time stamp high update register EMAC_PTPTSHUD 637 26 3 50 Ethernet PTP time stamp ...

Page 28: ... 656 27 8 3 DVP event status register DVP_ESTS 656 27 8 4 DVP interrupt enable register DVP_IENA 657 27 8 5 DVP interrupt status register DVP_ISTS 657 27 8 6 DVP interrupt clear register DVP_ICLR 657 27 8 7 DVP embedded synchronization code register DVP_SCR 658 27 8 8 DVP embedded synchronization unmask register DVP_SUR 658 27 8 9 DVP crop window start register DVP_CWST 659 27 8 10 DVP crop window...

Page 29: ...ter ACTR 670 28 4 7 FIFO status register FIFOSTS 670 28 4 8 Control register 2 CTRL2 671 28 4 9 Command status register CMDSTS 671 28 4 10 Read status register RSTS 671 28 4 11 Flash size register FSIZE 672 28 4 12 XIP command word 0 XIP CMD_W0 672 28 4 13 XIP command word 1 XIP CMD_W1 672 28 4 14 XIP command word 2 XIP CMD_W2 673 28 4 15 XIP command word 3 XIP CMD_W3 674 28 4 16 Revision register...

Page 30: ...m x peripheral address register DMA_SxPADDR x 1 8 695 29 5 8 DMA stream x memory 0 address register DMA_SxM0ADDR x 1 8 696 29 5 9 DMA stream x memory 1 address register DMA_SxM1ADDR x 1 8 696 29 5 10 DMA stream x FIFO control register DMA_SxFCTRL x 1 8 696 29 5 11 DMA linked table control register DMA_SxLLCTRL 697 29 5 12 DMA linked table pointer register DMA_SxLLP x 1 8 697 29 5 13 DMA 2D transfe...

Page 31: ...r interrupt clear flag register DMA_ MUXGCLR 701 30 Debug DEBUG 702 30 1 Debug introduction 702 30 2 Debug and Trace 702 30 3 I O pin control 702 30 4 DEGUB registers 702 30 4 1 DEBUG device ID DEBUG_IDCODE 703 30 4 2 DEBUG control register DEBUG_CTRL 703 30 4 3 DEBUG APB1 pause register DEBUG_ APB1_PAUSE 704 30 4 4 DEBUG APB2 pause register DEBUG_ APB2_PAUSE 705 30 4 5 MCU SERIES ID register DEBU...

Page 32: ...m data area erase process 104 Figure 5 6 System data area programming process 105 Figure 6 1 GPIO basic structure 116 Figure 6 2 IOMUX structure 118 Figure 8 1 External interrupt Event controller block diagram 146 Figure 9 1 DMA block diagram 149 Figure 9 2 Re arbitrate after request acknowledge 151 Figure 9 3 PWIDTH byte MWIDTH half word 151 Figure 9 4 PWIDTH half word MWIDTH word 152 Figure 9 5 ...

Page 33: ...wire unidirectional receive only in SPI slave mode 223 Figure 13 5 Single wire bidirectional half duplex mode 224 Figure 13 6 Master full duplex communications 228 Figure 13 7 Slave full duplex communications 229 Figure 13 8 Master half duplex transmit 229 Figure 13 9 Slave half duplex receive 229 Figure 13 10 Slave half duplex transmit 230 Figure 13 11 Master half duplex receive 230 Figure 13 12 ...

Page 34: ...4 32 Example of reset mode 265 Figure 14 33 Example of suspend mode 265 Figure 14 34 Example of trigger mode 265 Figure 14 35 Master slave timer connection 266 Figure 14 36 Using master timer to start slave timer 266 Figure 14 37 Starting master and slave timers synchronously by an external trigger 267 Figure 14 38 Block diagram of general purpose TMR9 12 278 Figure 14 39 Block diagram of general ...

Page 35: ...gnment 366 Figure 18 13 Block diagram of master salve mode 367 Figure 18 14 Regular simultaneous mode 369 Figure 18 15 Regular simultaneous mode 369 Figure 18 16 Alternate preempted trigger mode 370 Figure 18 17 Regular shift mode 370 Figure 18 18 Regular shift mode and DMA mode 2 371 Figure 19 1 DAC1 DAC2 block diagram 388 Figure 19 2 LFSR register calculation algorithm 390 Figure 19 3 Triangular...

Page 36: ... 2 read access 512 Figure 24 6 NOR PSRAM mode 2 write access 513 Figure 24 7 NOR PSRAM mode A read access 514 Figure 24 8 NOR PSRAM mode A write access 515 Figure 24 9 NOR PSRAM mode B read access 516 Figure 24 10 NOR PSRAM mode B write access 517 Figure 24 11 NOR PSRAM mode C read access 518 Figure 24 12 NOR PSRAM mode C write access 519 Figure 24 13 NOR PSRAM mode D read access 520 Figure 24 14 ...

Page 37: ...rigger output to TMR2 ITR1 connection 605 Figure 26 17 PPS output 606 Figure 26 18 Ethernet interrupts 607 Figure 27 1 DVP block diagram 640 Figure 27 2 CMOS video camera output in Frame start type 641 Figure 27 3 CMOS video camera output in Frame valid type 641 Figure 27 4 FS FE LS LE frame composition 642 Figure 27 5 SAV EAV frame composition 643 Figure 27 6 Block diagram in single frame capture...

Page 38: ...29 3 Re arbitrate after Request Acknowledge 678 Figure 29 4 Example of packing mechanism 678 Figure 29 5 Example of unpacking mechanism 679 Figure 29 6 Example of PINCOS 679 Figure 29 7 Descriptor format 680 Figure 29 8 Linked list pointers 680 Figure 29 9 Example of a 2D transfer source side is managed by a peripheral controller 681 Figure 29 10 Example of a 2D transfer destination side is manage...

Page 39: ...gister 125 Table 6 5 Port E multiplexed function configuration with GPIOE_MUX register 127 Table 6 6 Port F multiplexed function configuration with GPIOF_MUX register 129 Table 6 7 Port G multiplexed function configuration with GPIOG_MUX register 131 Table 6 8 Port H multiplexed function configuration with GPIOH_MUX register 133 Table 6 9 Pins owned by hardware 133 Table 6 10 GPIO register map and...

Page 40: ...ary output channel CxOUT and CxCOUT control bits with brake function 327 Table 15 1 Minimum and maximum timeout value when PCLK1 72 MHz 333 Table 15 2 WWDT register map and reset value 333 Table 16 1 WDT timeout period LICK 40kHz 336 Table 16 2 WDT register and reset value 336 Table 17 1 RTC register map and reset values 339 Table 17 2 ERTC low power mode wakeup 345 Table 17 3 Interrupt control bi...

Page 41: ...select register 517 Table 24 23 Mode C SRAM NOR Flash chip select timing register 518 Table 24 24 Mode C SRAM NOR Flash write timing register 518 Table 24 25 Mode D SRAM NOR Flash chip select register XMC_BK1CTRL configuration 519 Table 24 26 Mode D SRAM NOR Flash chip select timing register 520 Table 24 27 Mode D SRAM NOR Flash write timing register 520 Table 24 28 Multiplexed mode SRAM NOR Flash...

Page 42: ...ace signal encode 580 Table 26 3 Receive interface signal encode 580 Table 26 4 Ethernet peripheral pin configuration black default red remapping signals 582 Table 26 5 Destination address filtering 585 Table 26 6 Source address filtering 585 Table 26 7 Receive descriptor 0 599 Table 26 8 Ethernet register map and its reset values 607 Table 27 1 DVP pin use in hardware synchronization mode 642 Tab...

Page 43: ...er external memory controller XMC USB2 0 full speed interfaces Ethernet MAC parallel digital camera interface HICK with automatic clock calibration ACC 12 bit ADC 12 bit DAC programmable voltage monitor PVM and other peripherals Cortex M4F processer supports enhanced high performance DSP instruction set including extended single cycle 16 bit 32 bit multiply accumulator MAC dual 16 bit MAC instruct...

Page 44: ...2 Bus Freq Max 144 MHz APB1 Bus Freq Max 144 MHz CRM TMR2 5 TMR3 4 TMR6 7 TMR12 13 14 ERTC WWDT PWC USART2 3 UART4 5 7 8 CAN1 2 DAC Controller DAC1 DAC2 WDT EXINT GPIO A B C D E F G H TMR1 8 20 USART1 6 I2 C1 2 3 TMR9 10 11 ADCIF ADC2 ADC1 ADC3 HICK 48 MHz LICK PLL Max 288 MHz LEXT 32KHz POR LVR PVM LDO 1 2V SWJTAG NVIC HCLK FCLK PCLK1 PCLK2 HEXT 4 25 MHz Temperature Sensor SDIO1 2 SPI1 I2 S1 SPI3...

Page 45: ...sponse to interruption Cortex M4F processor is based on ARMv7 M architecture supporting both Thumb instruction set and DSP instruction set Figure 1 2 shows the internal block diagram of Cortex M4F processor Please refer to ARM Cortex M4 Technical Reference Manual for more information Figure 1 2 Internal block diagram of Cortex M4F NVIC MPU FPB DWT AHB AP Bus Matrix ITM Cortex M4F TPIU SW DP or SWJ...

Page 46: ...11 Page 46 Rev 2 03 Figure 1 3 Internal block diagram of AHB BusMatrix ARM Corter M4 ICODE DCODE SBUS DMA1 EDMA EMAC FLASH SRAM1 APB1 APB2 AHB1 SDIO1 SDIO2 XMC_ MEM EMAC QSPI1_ MEM QSPI2_ MEM DVP USBOTG1 USBOTG2 GPIO P M AHB BUS MATRIX SRAM2 DMA2 ...

Page 47: ...alias region total 32M bytes 0x2000_0000 0x2000_0001 0x2000_0002 0x2000_0003 0x2200_001C 1 2 3 4 5 6 7 0x2200_0018 0x2200_0014 0x2200_0010 0x2200_000C 0x2200_0008 0x2200_0004 0x2200_0000 0x200F_FFFC 0x200F_FFFD 0x200F_FFFE 0x200F_FFFF 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0x23FF_FFE0 0x23FF_FFE4 0x23FF_FFE8 0x23FF_FFEC 0x23F...

Page 48: ...00_0080 0 0x2000_0004 1 0x2200_0084 0 0x2000_0004 2 0x2200_0088 0 0x200F_FFFC 31 0x23FF_FFFC 0 Table 1 2 shows the mapping between bit band region and alias region in the peripheral area Table 1 2 Bit band address mapping in the peripheral area Bit band region Equivalent alias address 0x4000_0000 0 0x4200_0000 0 0x4000_0000 1 0x4200_0004 0 0x4000_0000 2 0x4200_0008 0 0x4000_0000 31 0x4200_007C 0 0...

Page 49: ...gu rable SVCall System service call via SWI instruction 0x0000_002C 4 Configu rable Debug Monitor Debug monitor 0x0000_0030 Reserved 0x0000_0034 5 Configu rable PendSV Pendable request for system service 0x0000_0038 6 Configu rable SysTick System tick timer 0x0000_003C 0 7 Configu rable WWDT Window watchdog timer 0x0000_0040 1 8 Configu rable PVM PVM from EXINT interrupt 0x0000_0044 2 9 Configu ra...

Page 50: ...gu rable TMR4 TMR4 global interrupt 0x0000_00B8 31 38 Configu rable I2C1_EVT I 2 C1 event interrupt 0x0000_00BC 32 39 Configu rable I2C1_ERR I 2 C1 error interrupt 0x0000_00C0 33 40 Configu rable I2C2_EVT I 2 C2 event interrupt 0x0000_00C4 34 41 Configu rable I2C2_ERR I 2 C2 error interrupt 0x0000_00C8 35 42 Configu rable SPI1 SPI1 global interrupt 0x0000_00CC 36 43 Configu rable SPI2_I2S2EXT SPI2...

Page 51: ...thernet wakeup interrupt through EXINT 0x0000_0138 63 70 Configu rable CAN2_TX CAN2 TX interrupt 0x0000_013C 64 71 Configu rable CAN2_RX0 CAN2 RX0 interrupt 0x0000_0140 65 72 Configu rable CAN2_RX1 CAN2 RX1 interrupt 0x0000_0144 66 73 Configu rable CAN2_SE CAN2 status error interrupt 0x0000_0148 67 74 Configu rable OTGFS1 OTGFS1 CAN2 status error interrupt 0x0000_014C 68 75 Configu rable DMA1 chan...

Page 52: ...le TMR20_CH TMR20 channel interrupt 0x0000_01EC 108 115 Configu rable DMA2 channel0 DMA2 channel0 global interrupt 0x0000_01F0 109 116 Configu rable DMA2 channel1 DMA2 channel1 global interrupt 0x0000_01F4 110 117 Configu rable DMA2 channel2 DMA2 channel2 global interrupt 0x0000_01F8 111 118 Configu rable DMA2 channel3 DMA2 channel3 global interrupt 0x0000_01FC 112 119 Configu rable DMA2 channel4 ...

Page 53: ...ction time Cortex M4F uses a full stack that increases downward so the initial value of the main stack pointer MSP must be the end address of the stack memory plus 1 For example if the stack area is set between 0x2000_7C00 and 0x2000_7FFF then the initial value of MSP must be defined as 0x2000_8000 The vector table follows the initial value of MSP Cortex M4F operates in Thumb state and thus each v...

Page 54: ...mory from which CODE starts BOOT1 BOOT0 00 10 CODE starts from the main Flash memory BOOT1 BOOT0 01 CODE starts from Boot code BOOT1 BOOT0 11 CODE starts from SRAM After a system reset or when leaving from Standby mode the pin values of both BOOT1 and BOOT0 will be relatched If on chip SRAM mode is used the BOOT state is locked In this case it is impossible to select another boot mode even after a...

Page 55: ...ved 1 3 Device characteristics information Table 1 5 List of abbreviations for registers Register abbr Base address Reset value F_SIZE 0x1FFF F7E0 0xXXXX UID 31 0 0x1FFF F7E8 0xXXXX XXXX UID 63 32 0x1FFF F7EC 0xXXXX XXXX UID 95 64 0x1FFF F7F0 0xXXXX XXXX 1 3 1 Flash memory size register This register contains the information about Flash memory size Bit Abbr Reset value Type Description Bit 15 0 F_...

Page 56: ..._0000 0x3FFF_FFFF 0x4000_0000 0x5FFF_FFFF External memory XMC NOR PSRAM SRAM NAND 0xB000_0000 0xA000_3000 0xE000_0000 0xFFFF_FFFF Reserved 0x6000_0000 0xA000_0000 XMC and QSPI1 2 Reg 0x9FFF_FFFF 0xA000_2FFF Reserved Cortex M4 Internal Peripherals 0xE00F_FFFF 0xE010_0000 Reserved 0x1000_FFFF 0x1001_0000 0x1FFE_FFFF External memory QSPI1 0x9000_0000 0x8FFF_FFFF External memory QSPI2 0xBFFF_FFFF 0xC0...

Page 57: ...0x0800 FFFF Block 1 Sector 16 0x0801 0000 0x0801 0FFF Sector 31 0x0801 F000 0x0801 FFFF Block 31 Sector 496 0x081F 0000 0x081F 0FFF Sector 511 0x081F F000 0x081F FFFF Bank 2 1984 KB Block 32 Sector 512 0x0820 0000 0x0820 0FFF Sector 527 0x0820 F000 0x0820 FFFF Block 62 Sector 992 0x083E 0000 0x083E 0FFF Sector 1007 0x083E F000 0x083E FFFF Information block 16 KB boot loader 0x1FFF 0000 0x1FFF 3FFF...

Page 58: ... 0x0800 07FF Sector 1 0x0800 0800 0x0800 0FFF Sector 2 0x0800 1000 0x0800 17FF Sector 31 0x0800 F800 0x0800 FFFF Block 1 Sector 32 0x0801 0000 0x0801 07FF Sector 63 0x0801 F800 0x0801 FFFF Block 7 Sector 224 0x0807 0000 0x0807 07FF Sector 255 0x0807 F800 0x0807 FFFF Bank 2 512 KB Block 8 Sector 256 0x0808 0000 0x0808 07FF Sector 287 0x0808 F800 0x0808 FFFF Block 15 Sector 480 0x080F 0000 0x080F 07...

Page 59: ...tes half words 16 bit or words 32 bit In addition AT32F435 437 also provide a special mode that enables a dynamic switch between 128 KB minimum and 512 KB maximum This is done by setting the EOPB0 bit In 512 KB mode Flash memory size zero wait sate is limited to 128 KB while in 128 KB extension mode the zero wait state Flash size is limited to 512 KB On chip SRAM is divided into SRAM1 and SRAM2 Th...

Page 60: ...002 37FF Reserved 0x4002 3000 0x4002 33FF CRC APB2 0x4001 8000 0x4001 FFFF Reserved 0x4001 7C00 0x4001 7FFF I2S3EXT 0x4001 7800 0x4001 7BFF I2S2EXT 0x4001 7400 0x4001 77FF ACC 0x4001 4C00 0x4001 73FF TMR20 timer 0x4001 4800 0x4001 4BFF TMR11 timer 0x4001 4400 0x4001 47FF TMR10 timer 0x4001 4000 0x4001 43FF TMR9 timer 0x4001 3C00 0x4001 3FFF EXINT 0x4001 3800 0x4001 3BFF SCFG 0x4001 3400 0x4001 37F...

Page 61: ...000 4000 0x4000 43FF Reserved 0x4000 3C00 0x4000 3FFF SPI3 I2S3 0x4000 3800 0x4000 3BFF SPI2 I2S2 0x4000 3400 0x4000 37FF Reserved 0x4000 3000 0x4000 33FF Watchdog timer WDT 0x4000 2C00 0x4000 2FFF Window watchdog timer WWDT 0x4000 2800 0x4000 2BFF ERTC 0x4000 2400 0x4000 27FF Reserved 0x4000 2000 0x4000 23FF TMR14 timer 0x4000 1C00 0x4000 1FFF TMR13 timer 0x4000 1800 0x4000 1BFF TMR12 timer 0x400...

Page 62: ...omain CPU WDT LICK Memory Digital Peripherals PLL HICK PVM sleeping deepsleep LEXT ERTC POR_BPD BPR Registers CRM BPDC Register DAC ADC Temp Sensor 3 2 Main Features Three power domains VDD VDDA domain 1 2 V domain and battery powered domain Three types of power saving modes Sleep mode Deepsleep mode and Standby mode Internal voltage regulator supplies 1 2 V voltage source for the core domain Powe...

Page 63: ...selected with the PVMSEL 2 0 After PVM is enabled the comparison result between VDD and the programmed threshold is indicated by the PVMOF bit in the PWC_CTRLSTS register with the hysteresis voltage VHYS_P being 100 mv The PVM interrupt will be generated through the EXTI line 16 when VDD rises above the PVM threshold Figure 3 3 PVM threshold and output PVMOF VDD 100 mV hysteresis VDET_P VHYS_P VDE...

Page 64: ...o VBAT pin to ensure that ERTC can work normally 1 When the battery powered domain is powered by VDD the PC13 can be used as a general purpose I O tamper pin ERTC calibration clock ERTC alarm or second output while the PC14 and PC15 can be used as a GPIO or LEXT pin As an I O port PC13 PC14 and PC15 must be limited below 2 MHz and to the maximum load of 30 pF and these I O ports must not be used a...

Page 65: ...nd both HICK and HEXT oscillators are disabled The LDO supplies power to the 1 2 V domain in normal mode or low power mode All I O pins keep the same state as in Run mode SRAM and register contents are preserved 1 When the Sleep mode is entered by executing a WFI instruction the interrupt generated on any external interrupt line in Interrupt mode can wake up the system from Deepsleep mode 2 When t...

Page 66: ...e all I O pins remain in a high impedance state except reset pins TAMPER pins that are set as anti tamper or calibration output and the wakeup pins enabled The MCU leaves the Standby mode when an external reset NRST pin a WDT reset a rising edge on the WKUP pin or the rising edge of an RTC alarm even occurs Debug mode By default the debug connection is lost if the MCU enters Deepsleep mode or Stan...

Page 67: ... Low power mode select when Cortex M4F sleepdeep 0 Enter DEEPSLEEP mode 1 Enter Standby mode Bit 0 VRSEL 0x0 rw LDO state select in Deepsleep mode 0 Enabled 1 Low power consumption mode 3 7 2 Power control status register PWC_CTRLSTS Additional APB cycles are needed to read this register versus a standard APB read Bit Name Reset value Type Description Bit 31 10 Reserved 0x000000 resd Kept at its d...

Page 68: ... by POR LVR or by setting the CLSWEF bit A wakeup event is generated by one of the following When the rising edge on the Standby wakeup pin occurs When the ERTC alarm event occurs If the Standby wakeup pin is enabled when the Standby wakeup pin level is high 3 7 3 LDO output voltage select register PWC_LDOOV Bit Name Reset value Type Description Bit 31 3 Reserved 0x0000 0000 resd Kept at its defau...

Page 69: ...PB1 2 peripheral Max 288MHz to TMRx CLK Peripheral clock enable APB1 2 Divider 1 2 4 8 16 x1 x 2 AHB APB1 and APB2 all support multiple frequency division The AHB domain has a maximum of 288 MHz and both APB1 and APB2 are up to 144 MHz 4 1 1 Clock sources High speed external oscillator HEXT The HEXT includes two clock sources crystal ceramic resonator and bypass clock The HEXT crystal ceramic reso...

Page 70: ...Hz It acts as a low power clock source that can be kept running in Deepsleep mode and Standby mode for watchdog and auto wakeup unit The LICK clock signal is not released before it becomes stable 4 1 2 System clock After a system reset the HICK oscillator is selected as system clock The system clock can make flexible switch among HICK oscillator HEXT oscillator and PLL clock However a switch from ...

Page 71: ...he microcontroller allows the internal clock signal to be output to external CLKOUT1 2 pins That is ADCCLK USB48M SCLK LICK LEXT HICK HEXT PLLCLK can be used as CLKOUT1 2 clocks When being used as the CLKOUT1 2 clock output pin the corresponding GPIO port registers must be configured accordingly 4 1 7 Interrupts The microcontroller specifies a stable flag for each clock source As a result when a c...

Page 72: ...ve to be accessed by bytes 8 bits half words 16 bits or words 32 bits Table 4 1 CRM register map and reset values Register Offset Reset value CRM_CTRL 0x000 0x0000 XX83 CRM_PLLCFG 0x004 0x0003 3002 CRM_CFG 0x008 0x0000 0000 CRM_CLKINT 0x00C 0x0000 0000 CRM_AHBRST1 0x010 0x0000 0000 CRM_AHBRST2 0x014 0x0000 0000 CRM_AHBRST3 0x018 0x0000 0000 CRM_APB1RST 0x020 0x0000 0000 CRM_APB2RST 0x024 0x0000 00...

Page 73: ... HEXT becomes stable 0 HEXT is not ready 1 HEXT is ready Bit 16 HEXTEN 0x0 rw High speed external crystal enable This bit is set and cleared by software It can also be cleared by hardware when entering Standby or Deepsleep mode When the HEXT clock is used as the system clock this bit cannot be cleared 0 OFF 1 ON Bit 15 8 HICKCAL 0xXX rw High speed internal clock calibration The default value of th...

Page 74: ...0x0 resd Kept at its default value Bit 18 16 PLL_FR 0x3 rw PLL post division PLL_FR range 2 5 000 Reserved Do not use 001 Reserved Do not use 010 PLL post division 4 011 PLL post division 8 100 PLL post division 16 101 PLL post division 32 Others Reserved Do not use Attention should be paid to the correlation between the PLL_FR value and post division factor Bit 15 Reserved 0x0 resd Kept at its de...

Page 75: ...t 29 27 CLKOUT2DIV1 0x0 rw Clock output2 division1 0xx CLKOUT2 100 CLKOUT2 2 101 CLKOUT2 3 110 CLKOUT2 4 111 CLKOUT2 5 Bit 26 24 USBDIV 0x0 rw Clock output1 division1 0xx CLKOUT1 100 CLKOUT1 2 101 CLKOUT1 3 110 CLKOUT1 4 111 CLKOUT1 5 Bit 23 Reserved 0x0 resd Kept at its default value Bit 22 21 CLKOUT1_SEL 0x0 rw Clock output1 selection This field is set and cleared by software 00 HICK selected 01...

Page 76: ...y 4 110 divided by 8 111 divided by 16 Note The software must set these bits correctly to ensure that the APB1 clock frequency does not exceed 144 MHz Bit 9 8 Reserved 0x0 resd Kept at its default value Bit 7 4 AHBDIV 0x0 rw AHB division 0xxx SCLK not divided 1000 SCLK divided by 2 1100 SCLK divided by 64 1001 SCLK divided by 4 1101 SCLK divided by 128 1010 SCLK divided by 8 1110 SCLK divided by 2...

Page 77: ... 1 by software to clear HICKSTBLF 0 No effect 1 Clear Bit 17 LEXTSTBLFC 0x0 wo LEXT stable flag clear Writing 1 by software to clear LEXTSTBLF 0 No effect 1 Clear Bit 16 LICKSTBLFC 0x0 wo LICK stable flag clear Writing 1 by software to clear LICKSTBLF 0 No effect 1 Clear Bit 15 13 Reserved 0x0 resd Kept at its default value Bit 12 PLLSTBLIEN 0x0 rw PLL stable interrupt enable 0 Disabled 1 Enabled ...

Page 78: ... default value Bit 29 OTGFS2RST 0x0 rw OTGFS2 reset 0 Does not reset the OTGFS2 1 Reset the OTGFS2 Bit 28 26 Reserved 0x0 resd Kept at its default value Bit 25 EMACRST 0x0 rw EMAC reset 0 Does not reset the Ethernet MAC 1 Reset the Ethernet MAC Bit 24 DMA2RST 0x0 rw DMA2 reset 0 Does not reset DMA2 1 Reset DMA2 Bit 23 Reserved 0x0 resd Kept at its default value Bit 22 DMA1RST 0x0 rw DMA1 reset 0 D...

Page 79: ...rved 0x0 resd Kept at its default value Bit 7 OTGFS1RST 0x0 rw OTGFS1 reset 0 Does not reset OTGFS1 1 Reset OTGFS1 Bit 6 1 Reserved 0x0 resd Kept at its default value Bit 0 DVPRST 0x0 rw DVP reset 0 Does not reset DVP 1 Reset DVP 4 3 7 APB peripheral reset register3 CRM_APBRST3 Access 0 wait state accessible by words half words and bytes Bit Name Reset value Type Description Bit 31 16 Reserved 0x0...

Page 80: ...x0 rw UART5 reset 0 Does not reset UART5 1 Reset UART5 Bit 19 UART4RST 0x0 rw UART4 reset 0 Does not reset UART4 1 Reset UART4 Bit 18 USART3RST 0x0 rw USART3 reset Set and cleared by software 0 Does not reset USART3 1 Reset USART3 Bit 17 USART2RST 0x0 rw USART2 reset 0 Does not reset USART2 1 Reset USART2 Bit 16 Reserved 0x0 resd Kept at its default value Bit 15 SPI3RST 0x0 rw SPI3 reset 0 Does no...

Page 81: ...served 0x0 resd Kept at its default value Bit 18 TMR11RST 0x0 rw Timer11 reset 0 Does not reset Timer11 1 Reset Timer11 Bit 17 TMR10RST 0x0 rw Timer10 reset 0 Does not reset Timer10 1 Reset Timer10 Bit 16 TMR9RST 0x0 rw Timer9 reset 0 Does not reset Timer9 1 Reset Timer9 Bit 15 Reserved 0x0 resd Kept at its default value Bit 14 SCFGRST 0x0 rw SCFG reset 0 Does not reset SCFG 1 Reset SCFG Bit 13 SP...

Page 82: ...enable 0 Disabled 1 Enabled Note In RMII mode if this clock is enabled then MAC RMII clock is enabled as well Bit 25 EMACEN 0x0 rw EMAC clock enable 0 Disabled 1 Enabled Bit 24 DMA2EN 0x0 rw DMA2 clock enable 0 Disabled 1 Enabled Bit 23 Reserved 0x0 resd Kept at its default value Bit 22 DMA1EN 0x0 rw DMA1 clock enable 0 Disabled 1 Enabled Bit 21 EDMAEN 0x0 rw EDMA clock enable 0 Disabled 1 Enabled...

Page 83: ... OTGFS1 clock enable 0 Disabled 1 Enabled Bit 6 1 Reserved 0x0 resd Kept at its default value Bit 0 DVPEN 0x0 rw DVP clock enable 0 Disabled 1 Enabled 4 3 12 APB1 peripheral clock enable register3 CRM_AHBEN3 Access 0 wait state accessible by words half words and bytes Bit Name Reset value Type Description Bit 31 16 Reserved 0x00 resd Kept at its default value Bit 15 SDIO2EN 0x0 rw SDIO2 clock enab...

Page 84: ...x0 rw I2C2 clock enable 0 Disabled 1 Enabled Bit 21 I2C1EN 0x0 rw I2C1 clock enable 0 Disabled 1 Enabled Bit 20 UART5EN 0x0 rw UART5 clock enable 0 Disabled 1 Enabled Bit 19 UART4EN 0x0 rw UART4 clock enable 0 Disabled 1 Enabled Bit 18 USART3EN 0x0 rw USART3 clock enable 0 Disabled 1 Enabled Bit 17 USART2EN 0x0 rw USART2 clock enable 0 Disabled 1 Enabled Bit 16 Reserved 0x0 resd Kept at its defaul...

Page 85: ... 1 Enabled 4 3 14 APB2 peripheral clock enable register CRM_AHB2EN Access 0 wait state accessible by words half words and bytes Bit Name Reset value Type Description Bit 31 30 Reserved 0x0 resd Kept at its default value Bit 29 ACCEN 0x0 rw ACC clock enable 0 Disabled 1 Enabled Bit 28 21 Reserved 0x0 resd Kept at its default value Bit 20 TMR20EN 0x0 rw Timer20 clock enable 0 Disabled 1 Enabled Bit ...

Page 86: ...0 Disabled 1 Enabled Bit 0 TMR1EN 0x0 rw Timer1 clock enable 0 Disabled 1 Enabled 4 3 15 APB peripheral clock enable in low power mode register1 CRM_AHBLPEN1 Access 0 wait state accessible by words half words and bytes Bit Name Reset value Type Description Bit 31 30 Reserved 0x0 resd Kept at its default value Bit 29 OTGFS2LPEN 0x1 rw OTGFS2 clock enable in sleep mode 0 Disabled 1 Enabled Bit 28 EM...

Page 87: ...ock enable in sleep mode 0 Disabled 1 Enabled Bit 6 GPIOGLPEN 0x1 rw IO port G clock enable in sleep mode 0 Disabled 1 Enabled Bit 5 GPIOFLPEN 0x1 rw IO port F clock enable in sleep mode 0 Disabled 1 Enabled Bit 4 GPIOELPEN 0x1 rw IO port E clock enable in sleep mode 0 Disabled 1 Enabled Bit 3 GPIODLPEN 0x1 rw IO port D clock enable in sleep mode 0 Disabled 1 Enabled Bit 2 GPIOCLPEN 0x1 rw IO port...

Page 88: ..._AHB1LPEN Access 0 wait state accessible by words half words and bytes Bit Name Reset value Type Description Bit 31 UART8LPEN 0x1 rw UART8 clock enable in sleep mode 0 Disabled 1 Enabled Bit 30 UART7LPEN 0x1 rw UART7 clock enable in sleep mode 0 Disabled 1 Enabled Bit 29 DACLPEN 0x1 rw DAC interface clock enable in sleep mode 0 Disabled 1 Enabled Bit 28 PWCLPEN 0x1 rw Power interface clock enable ...

Page 89: ...sleep mode 0 Disabled 1 Enabled Bit 5 TMR7LPEN 0x1 rw Timer 7 clock enable in sleep mode 0 Disabled 1 Enabled Bit 4 TMR6LPEN 0x1 rw Timer 6 clock enable in sleep mode 0 Disabled 1 Enabled Bit 3 TMR5LPEN 0x1 rw Timer 5 clock enable in sleep mode 0 Disabled 1 Enabled Bit 2 TMR4LPEN 0x1 rw Timer 4 clock enable in sleep mode 0 Disabled 1 Enabled Bit 1 TMR3LPEN 0x1 rw Timer 3 clock enable in sleep mode...

Page 90: ...1 clock enable in sleep mode 0 Disabled 1 Enabled Bit 3 2 Reserved 0x0 resd Kept at its default value Bit 1 TMR8LPEN 0x1 rw TMR8 timer clock enable in sleep mode 0 Disabled 1 Enabled Bit 0 TMR1LPEN 0x1 rw TMR1 timer clock enable in sleep mode 0 Disabled 1 Enabled 4 3 20 Battery powered domain control register CRM_BPDC Access 0 to 3 wait states accessible by words half words or bytes Wait states ar...

Page 91: ...le by words half words or bytes Wait states are inserted in the case of consecutive accesses to this register Bit Name Reset value Type Description Bit 31 LPRSTF 0x0 ro Low power reset flag Set by hardware Cleared by writing to the RSTFC bit 0 No low power reset occurs 1 Low power reset occurs Bit 30 WWDTRSTF 0x0 ro Window watchdog timer reset flag Set by hardware Cleared by writing to the RSTFC b...

Page 92: ...utput1 division2 0xxx Clock output 1000 Clock output divided by 2 1001 Clock output divided by 4 1010 Clock output divided by 8 1011 Clock output divided by 16 1100 Clock output divided by 64 1101 Clock output divided by 128 1110 Clock output divided by 256 1111 Clock output divided by 512 Bit 23 20 Reserved 0x0 resd Kept its default value Bit 19 16 CLKOUT2_SEL2 0x0 rw Clock output2 sel2 0000 USB ...

Page 93: ... 6 5 1011 PLL clock divided by 6 1100 PLL clock divided by 7 1101 1111 Reserved Bit 11 10 Reserved 0x0 resd Kept at its default value Bit 9 EMAC_PPS_SEL 0x0 rw Ethernet pulse width select 0 Pulse width is 125 ms 1 Pulse width is 1 system clock Bit 8 CLK1_TO_TMR 0x0 rw CLKOUT1 internal connected to timer 10 channel 1 0 Disconnected 1 Connected Bit 7 6 Reserved 0x0 resd Kept at its default value Bit...

Page 94: ...ank 2 1984 KB including 31 sectors with 16 sectors in each and 4 KB per sector User system data area is 4 KB Table 5 1 Flash memory architecture 4032 K Bank Name Address range Main Flash memory Bank 1 2048 KB Sector 0 Sector 0 0x0800 0000 0x0800 0FFF Sector 1 0x0800 1000 0x0800 1FFF Sector 2 0x0800 2000 0x0800 2FFF Sector 15 0x0800 F000 0x0800 FFFF Sector 1 Sector 16 0x0801 0000 0x0801 0FFF Sector...

Page 95: ...t loader 0x1FFF 0000 0x1FFF 3FFF 512 B user option bytes 0x1FFF C000 0x1FFF C1FF Main Flash memory 256 KB has only bank 1 including four sectors with 32 sectors in each 2 K per sector User system data area is 512 B Table 5 3 Flash memory architecture 256 K Bank Name Address range Main Flash memory Bank 1 256 KB Sector 0 Sector 0 0x0800 0000 0x0800 07FF Sector 1 0x0800 0800 0x0800 0FFF Sector 2 0x0...

Page 96: ... Reserved Bit 3 BTOPT 0 When booting from main Flash memory if there is no boot loader in the bank 2 it will starts from bank 1 otherwise bank 2 1 When booting from main Flash memory it starts from bank 1 Bit 2 nSTDBY_RST 0 Reset occurs when entering Standby mode 1 No reset occurs when entering Standby mode Bit 1 nDEPSLP_RST 0 Reset occurs when entering Deepsleep mode 1 No reset occurs when enteri...

Page 97: ...128 KB sectors 0 Erase write protection is enabled 1 Erase write protection is disabled 31 24 nEPP5 7 0 Inverse code of nEPP5 7 0 0x1FFF_C018 7 0 EPP6 7 0 Flash erase write protection byte 6 stored in the FLASH_EPPS1 23 16 Bit 7 is reserved Bit 6 0 is used to protect the 2177 3200 KB of main Flash memory Each bit takes care of 128 KB sectors 0 Erase write protection is enabled 1 Erase write protec...

Page 98: ...0 0x1FFF_CFFC 7 0 Data2010 7 0 User data2010 15 8 nData2010 7 0 Inverse code of Data2010 7 0 23 16 Data2011 7 0 User data2011 31 24 nData2011 7 0 Inverse code of Data2011 7 0 Note In Flash memory below 4032 KB there are 256 bytes of user system data ranging from 0x1FFF_C000 to 0x1FFF_C1FF including 220 bytes of user data In 4032 KB Flash memory there are 2048 bytes of user system data ranging from...

Page 99: ...lock can be locked by setting the OPLK bit in the FLASH_CTRLx register 5 2 2 Erase operation Erase operation must be done before programming Flash memory erase includes sector erase block erase and mass erase Sector erase Any sector in the Flash memory can be erased with sector erase function independently Below should be followed during se erase Check the OBF bit in the FLASH_STSx register to con...

Page 100: ...LASH_STSx No Yes End Block erase Any block of Flash memory can be erased independently The following process is recommended Check the OBF bit in the FLASH_STSx register to confirm that there is no other programming operation in progress Write the block to be erased in the FLASH_ADDRx register Set the BANKERS and ERSTR bit in the FLASH_CTRLx register to enable block erase Wait until the OBF bit bec...

Page 101: ...d Mass erase Mass erase function can erase all the Flash memory The following process is recommended Check the OBF bit in the FLASH_STSx register to confirm that there is no other programming operation in progress Set the BANKERS and ERSTR bit in the FLASH_CTRLx register to enable mass erase Wait until the OBF bit becomes 0 in the FLASH_STSx register Read the EPPERR bit and ODF bit in the FLASH_ST...

Page 102: ... no other programming operation in progress Set the FPRGM bit in the FLASH_CTRLx register so that the Flash memory programming instructions can be received Write the data word half word byte to be programmed to the designated address Wait until the OBF bit in the FLASH_STSx register becomes 0 read the EPPERR PRGMERR and ODF bit to verify the programming result Note 1 When the address to be written...

Page 103: ...ter reset user system data area is protected by default Write and erase operations can be performed only after the Flash memory is unlocked before the unlock operation for the user system data area Unlock procedure Flash memory block can be unlocked by writing KEY1 0x45670123 and KEY2 0xCDEF89AB to the FLASH_UNLOCK register When KEY1 0x45670123 and KEY2 0xCDEF89AB is written to the FLASH_USD_UNLOC...

Page 104: ... register to confirm that there is no other programming operation in progress Set the USDERS and ERSTR bit in the FLASH_CTRL register to enable erase operation Wait until the OBF bit becomes 0 in the FLASH_STS register Read the ODF bit in the FLASH_STSx register to verify the erase result Note Read operation to the Flash memory during programming will halt CPU until the completion of erase Figure ...

Page 105: ... user system data area can be received Write the data half word to be programmed to the designated address Wait until the OBF bit in the FLASH_STS register becomes 0 read the PRGMERR and ODF bit to verify the programming result Note Read operation to the Flash memory during programming will halt CPU until the completion of programming Figure 5 6 System data area programming process z OBF 0 Set the...

Page 106: ...nabled Table 5 6 Flash memory access limit Block Access limits In debug mode or boot from SRAM and boot loader Boot from main Flash memory Read Write Erase Read Write Erase Main Flash memory Not allowed Not allowed 1 2 Accessible External memory Not allowed Not allowed 2 Accessible User system data area Not allowed Accessible Accessible 1 Main Flash memory is cleared automatically by hardware only...

Page 107: ...5F6D24 to the SLIB_UNLOCK register and checking the SLIB_ULKF bit in the SLIB_MISC_STS register to verify if it is unlocked successfully and then writing the programmed value into the security library setting register Optional CRC check for security library code is based on a sector level The steps to enable security library are as follows Check the OBF bit in the FLASH_STS register to ensure that...

Page 108: ...SC_STS 0xD8 0x0100 0000 SLIB_SET_PWD 0xDC 0x0000 0000 SLIB_SET_RANGE0 0xE0 0x0000 0000 SLIB_SET_RANGE1 0xE4 0x0000 0000 SLIB_UNLOCK 0xF0 0x0000 0000 FLASH_CRC_CTRL 0xF4 0x0000 0000 FLASH_CRC_CHKR 0xF8 0x0000 0000 5 6 1 Flash performance select register FLASH_PSR Bit Abbr Reset value Type Description Bit 31 14 Reserved 0x00000 resd Kept at its default value Bit 13 NZW_BST_STS 0x0 ro Flash non zero ...

Page 109: ...ase program protected Flash memory address It is cleared by writing 1 Bit 3 Reserved 0x0 resd Kept at its default value Bit 2 PRGMERR 0x0 rw Programming error When the programming address is not 0xFFFF this bit is set by hardware It is cleared by writing 1 Bit 1 Reserved 0x0 resd Kept at its default value Bit 0 OBF 0x0 ro Operation busy flag When this bit is set it indicates that Flash memory oper...

Page 110: ...0x0 rw Flash program It indicates Flash program operation 5 6 6 Flash address register FLASH_ADDR Only used in Flash memory bank 1 Bit Register Reset value Type Description Bit 31 0 FA 0x0000 0000 wo Flash address Select the address of the blocks sectors to be erased 5 6 7 User system data register FLASH_USD Bit Register Reset value Type Description Bit 31 26 Reserved 0x00 resd Kept at its default...

Page 111: ...served 0x0000000 resd Kept at its default value Bit 5 ODF 0x0 rw Operation done flag This bit is set by hardware when Flash memory operations program erase is completed It is cleared by writing 1 Bit 4 EPPERR 0x0 rw Erase Program protection error This bit is set by hardware when programming the erase program protected Flash memory address It is cleared by writing 1 Bit 3 Reserved 0x0 resd Kept at ...

Page 112: ...egister2 FLASH_ADDR2 Only used in Flash memory bank 2 Bit Register Reset value Type Description Bit 31 0 FA 0x0000 0000 wo Flash address Select the address of the blocks sectors to be erased 5 6 14 Flash continue read register FLASH_CONTR Bit Register Reset value Type Description Bit 31 0 FCONTR_EN 0x0 rw Flash continue read enable 0 Flash continue read mode disabled 1 Flash continue read mode ena...

Page 113: ...8 Flash security library status register1 SLIB_STS1 Only used in Flash security library Bit Register Reset value Type Description Bit 31 16 SLIB_ES 0xFFFF ro Security library end sector 0 Sector 0 1 Sector 1 2 Sector 2 511 Sector 511 Bit 15 0 SLIB_SS 0xFFFF ro Security library start sector 0 Sector 0 1 Sector 1 2 Sector 2 511 Sector 511 5 6 19 Flash security library password clear register SLIB_PW...

Page 114: ... the startup password of security library Values of 0xFFFF_FFFF and 0x0000_0000 are invalid Note All these bits are write only and return 0 when being read 5 6 22 Security library address setting register0 SLIB_SET_RANGE0 Only used for Flash security library address setting Bit Register Reset value Type Description Bit 31 16 SLIB_ES_SET 0x000 wo Security library end sector setting Theses bits are ...

Page 115: ...ad 5 6 25 Flash CRC calibration control register FLASH_CRC_CTRL Only used in main Flash memory Bit Register Reset value Type Description Bit 31 CRC_STRT 0x0 wo CRC start Set this bit to enable user code or security library code CRC check This bit is cleared automatically after the hardware enables CRC Bit 30 24 Reserved 0x00 wo Kept at its default value Bit 23 12 CRC_SN 0x000 wo CRC sector number ...

Page 116: ... capability is configurable by software Each pin can be configured as external interrupt input Each pin can be locked 6 2 Function overview 6 2 1 GPIO structure Each of the GPIO pins can be configured by software as four input modes floating pull up pull down and analog input and four output modes open drain push pull alternate function push pull open drain output Each I O port bit can be programm...

Page 117: ...gth 001 Output mode large sourcing sinking strength 010 Output mode normal sourcing sinking strength 011 Output mode normal sourcing sinking strength 1xx Output mode Maximum sourcing sinking strength 00 or 11 Push Pull with pull up 01 0 01 Push Pull with pull down01 0 10 Open Drain without pull up pull down 01 1 000 Output mode normal sourcing sinking strength 001 Output mode large sourcing sinkin...

Page 118: ...multiplexed function mode push pull or open drain mode by setting GPIOx_CFGR or GPIOx_OMODE register In this case the pins are disconnected from GPIO controller and controlled by IOMUX controller instead To achieve bidirectional multiplexed function the port needs to be configured as multiplexed function modes push pull or open drain controlled by IOMUX controller Figure 6 2 IOMUX structure IO ESD...

Page 119: ..._CH3 TMR5_CH3 TMR9_CH1 USART2_TX PA3 TMR2_CH4 TMR5_CH4 TMR9_CH2 I2S2_MCK USART2_RX PA4 SPI1_CS I2S1_WS SPI3_CS I2S3_WS USART2_CK PA5 TMR2_CH1 TMR2_EXT TMR8_CH1C SPI1_SCK I2S1_CK PA6 TMR1_BRK TMR3_CH1 TMR8_BRK SPI1_MISO I2S2_MCK USART3_CTS PA7 TMR1_CH1C TMR3_CH2 TMR8_CH1C SPI1_MOSI I2S1_SDEXT PA8 CLKOUT1 TMR1_CH1 I2C3_SCL USART1_CK PA9 TMR1_CH2 I2C3_SMBA SPI2_SCK I2S2_CK USART1_TX PA10 TMR1_CH3 SPI...

Page 120: ... EVENTOUT PA5 USART6_RX QSPI2_IO2 SDIO2_D5 SDIO2_D1 XMC_D7 EVENTOUT PA6 TMR13_CH1 QSPI1_IO0 SDIO2_D2 SDIO1_C MD DVP_PIXCLK SDIO2_D6 EVENTOUT PA7 TMR14_CH1 QSPI1_IO1 EMAC_MII_RX_DV EMAC_RMII_CRS_DV XMC_SDN WE SDIO2_D3 SDIO2_D7 EVENTOUT PA8 USART2_TX OTG1_SOF SDIO1_D1 XMC_A4 EVENTOUT PA9 I2C1_SCL OTG1_VBU S SDIO1_D2 DVP_D0 EVENTOUT PA10 I2C1_SDA OTG1_ID DVP_D1 EVENTOUT PA11 USART6_TX CAN1_RX OTG1_D ...

Page 121: ... I2C1_SMBA SPI1_MOSI I2S1_SD SPI3_MOSI I2S3_SD USART1_CK PB6 TMR4_CH1 I2C1_SCL I2S1_MCK SPI4_CS I2S4_WS USART1_TX PB7 TMR4_CH2 TMR8_BRK I2C1_SDA SPI4_SCK I2S4_CK USART1_RX PB8 TMR2_CH1 TMR2_EXT TMR4_CH3 TMR10_CH1 I2C1_SCL SPI4_MISO PB9 IR_OUT TMR2_CH2 TMR4_CH4 TMR11_CH1 I2C1_SDA SPI2_CS I2S2_WS SPI4_MOSI I2S4_SD I2C2_SDA PB10 TMR2_CH3 I2C2_SCL SPI2_SCK I2S2_CK I2S3_MCK USART3_TX PB11 TMR2_CH4 TMR5...

Page 122: ...DIO1_D3 EVENTOUT PB6 UART5_TX CAN2_TX QSPI1_C S XMC_SD CS1 DVP_D5 SDIO1_D0 EVENTOUT PB7 QSPI2_IO1 XMC_NA DV DVP_VSYN C SDIO1_D0 EVENTOUT PB8 UART5_RX CAN1_RX QSPI2_C S EMAC_MII_TXD3 SDIO1_D4 DVP_D6 EVENTOUT PB9 UART5_TX CAN1_TX QSPI1_C S SDIO1_D5 DVP_D7 EVENTOUT PB10 QSPI1_CS QSPI1_IO 1 EMAC_MII_RX_ER SDIO1_D7 XMC_NOE EVENTOUT PB11 QSPI1_IO 0 EMAC_MII_TX_EN EMAC_RMII_TX_EN EVENTOUT PB12 USART3_CK ...

Page 123: ... SPI2_MISO I2S2_SDEXT PC3 SPI2_MOSI I2S2_SDEXT PC4 TMR9_CH 1 I2S1_MCK USART3_TX PC5 TMR9_CH 2 I2C1_SMBA USART3_RX PC6 TMR3_CH1 TMR8_CH 1 I2C1_SCL I2S2_MCK PC7 TMR3_CH2 TMR8_CH 2 I2C1_SDA SPI2_SCK I2S2_CK I2S3_MCK PC8 TMR3_CH3 TMR8_CH 3 I2S4_MCK TMR20_CH3 UART8_TX PC9 CLKOUT2 TMR3_CH4 TMR8_CH 4 I2C3_SDA UART8_RX PC10 TMR5_CH2 SPI3_SCK I2S3_CK USART3_TX PC11 TMR5_CH3 I2S3_SDEXT SPI3_MISO USART3_RX P...

Page 124: ...2 EMAC_MII_RXD0 EMAC_RMII_RX D0 XMC_SDCS0 SDIO2_CK XMC_NE4 EVENTOUT PC5 QSPI1_IO3 EMAC_MII_RXD1 EMAC_RMII_RX D1 XMC_SDCKE0 SDIO2_CMD XMC_NOE EVENTOUT PC6 USART6_TX XMC_A0 SDIO1_D6 DVP_D0 XMC_D1 EVENTOUT PC7 USART6_RX XMC_A1 SDIO1_D7 DVP_D1 EVENTOUT PC8 USART6_CK QSPI1_IO2 XMC_A2 SDIO1_D0 DVP_D2 EVENTOUT PC9 QSPI1_IO0 XMC_A3 OTG2_OE SDIO1_D1 DVP_D3 EVENTOUT PC10 UART4_TX QSPI1_IO1 SDIO1_D2 DVP_D8 E...

Page 125: ... I2S3_SDEXT SPI2_CS I2S2_WS PD1 SPI2_SCK I2S2_CK SPI2_CS I2S2_WS PD2 TMR3_EXT USART3_RTS_DE PD3 SPI2_SCK I2S2_CK SPI2_MISO USART2_CTS PD4 SPI2_MOSI I2S2_SDEXT USART2_RTS_DE PD5 USART2_TX PD6 SPI3_MOSI I2S3_SDEXT USART2_RX PD7 USART2_CK PD8 USART3_TX PD9 USART3_RX PD10 USART3_CK PD11 I2C2_SMBA USART3_CTS PD12 TMR4_CH1 I2C2_SCL USART3_RTS_DE PD13 TMR4_CH2 I2C2_SDA PD14 TMR4_CH3 I2C3_SCL PD15 TMR4_CH...

Page 126: ...TOUT PD5 XMC_A10 XMC_NWE EVENTOUT PD6 XMC_A11 XMC_NWAIT DVP_D10 EVENTOUT PD7 XMC_A12 XMC_NE1 XMC_NCE2 EVENTOUT PD8 EMAC_MII_RX_DV EMAC_RMII_CRS_DV XMC_D13 EVENTOUT PD9 EMAC_MII_RXD0 EMAC_RMII_RXD0 XMC_D14 EVENTOUT PD10 EMAC_MII_RXD1 EMAC_RMII_RXD1 XMC_D15 EVENTOUT PD11 QSPI1_IO0 XMC_A14 XMC_SDBA0 EMAC_MII_RXD2 XMC_A16 XMC CLE EVENTOUT PD12 QSPI1_IO1 XMC_A15 XMC_SDBA1 EMAC_MII_RXD3 XMC_A17 XMC ALE ...

Page 127: ..._CK TMR20_CH1 PE3 TMR3_CH 1 TMR20_CH2 PE4 CLKOUT 1 TMR3_CH 2 SPI4_CS I2S4_WS TMR20_CH1C PE5 TMR3_CH 3 TMR9_CH 1 SPI4_MISO TMR20_CH2C PE6 TMR3_CH 4 TMR9_CH 2 SPI4_MOSI I2S4_SDEXT TMR20_CH3C PE7 TMR1_EXT PE8 TMR1_CH1C UART4_TX PE9 TMR1_CH1 UART4_RX PE10 TMR1_CH2C PE11 TMR1_CH2 SPI4_CS I2S4_WS PE12 TMR1_CH3C SPI1_CS I2S1_WS SPI4_SCK I2S4_CK PE13 TMR1_CH3 SPI1_SCK I2S1_CK SPI4_MISO PE14 TMR1_CH4 SPI1_...

Page 128: ...MC_SDNCAS EMAC_MII_TXD3 XMC_A23 EVENTOUT PE3 XMC_A19 DVP_D9 EVENTOUT PE4 XMC_A20 DVP_D4 EVENTOUT PE5 XMC_A21 DVP_D6 EVENTOUT PE6 XMC_SDNRAS XMC_A22 DVP_D7 EVENTOUT PE7 UART7_RX QSPI2_IO0 XMC_D4 EVENTOUT PE8 UART7_TX QSPI2_IO1 XMC_D5 EVENTOUT PE9 QSPI2_IO2 XMC_D6 EVENTOUT PE10 UART5_TX QSPI2_IO3 XMC_D7 EVENTOUT PE11 UART5_RX XMC_D8 EVENTOUT PE12 XMC_D9 EVENTOUT PE13 XMC_D10 EVENTOUT PE14 XMC_D11 EV...

Page 129: ...n MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 PF0 I2C2_SDA PF1 I2C2_SCL PF2 TMR20_CH3 I2C2_SMBA PF3 TMR20_CH4 PF4 TMR20_CH1C PF5 TMR20_CH2C PF6 TMR20_CH4 TMR10_CH1 PF7 TMR20_BRK TMR11_CH1 PF8 PF9 TMR20_BRK PF10 TMR1_EXT TMR5_CH4 PF11 TMR20_EXT TMR8_EXT PF12 TMR20_CH1 TMR8_BRK PF13 TMR20_CH2 I2C3_SMBA PF14 TMR20_CH3 I2C3_SCL PF15 TMR20_CH4 I2C3_SDA ...

Page 130: ...MC_A3 EVENTOUT PF4 XMC_A4 EVENTOUT PF5 XMC_A5 EVENTOUT PF6 UART7_RX QSPI1_IO3 XMC_NIORD EVENTOUT PF7 UART7_TX QSPI1_IO2 XMC_NREG EVENTOUT PF8 TMR13_CH1 QSPI1_IO0 XMC_NIOWR EVENTOUT PF9 TMR14_CH1 QSPI1_MOSI_IO1 XMC_CD EVENTOUT PF10 QSPI1_SCK XMC_INTR DVP_D11 EVENTOUT PF11 XMC_SDNRAS DVP_D12 EVENTOUT PF12 XMC_A6 EVENTOUT PF13 XMC_A7 EVENTOUT PF14 XMC_A8 EVENTOUT PF15 XMC_A9 EVENTOUT ...

Page 131: ...UX register Pin MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 PG0 TMR20_CH1C SPI1_MISO PG1 TMR20_CH2C SPI1_MOSI I2S1_SDEXT PG2 TMR20_CH3C PG3 TMR20_BRK PG4 PG5 TMR20_EXT PG6 PG7 PG8 QSPI2_CS PG9 PG10 QSPI2_IO2 PG11 QSPI2_IO3 SPI4_SCK I2S4_CK PG12 QSPI2_IO1 SPI4_MISO PG13 QSPI2_SCK SPI4_MOSI I2S4_SDEXT PG14 QSPI2_IO0 SPI4_CS I2S4_WS PG15 ...

Page 132: ... DVP_D12 EVENTOUT PG7 USART6_CK XMC_INT3 DVP_D13 EVENTOUT PG8 USART6_RTS_DE EMAC_PPS_OUT XMC_SDCLK EVENTOUT PG9 USART6_RX QSPI1_IO2 XMC_NE2 XMC_NCE3 DVP_VSY NC EVENTOUT PG10 XMC_NE3 XMC_NCE4_1 DVP_D2 EVENTOUT PG11 CAN2_RX EMAC_MII_TX_EN EMAC_RMII_TX_EN XMC_NCE4_2 DVP_D3 EVENTOUT PG12 USART6_RTS_DE CAN2_TX XMC_NE4 EVENTOUT PG13 USART6_CTS EMAC_MII_TXD0 EMAC_RMII_TXD0 XMC_A24 EVENTOUT PG14 USART6_TX...

Page 133: ...eed of GPIO status configuration 6 2 11 IOMUX map priority The unique peripheral multiplexed function can be configured through the GPIOx_MUXL GPIOx_MUXH register except individual pins that may be directly owned by hardware Some pins have been directly owned by specific hardware feature whatever GPIO configuration Table 6 9 Pins owned by hardware Pin Enable bit Description PA0 PWC_CTRLSTS 8 1 Onc...

Page 134: ...000 A GPIOx_PULL x B C F 0x0C 0x0000 0100 B 0x0000 0000 GPIOx_IDT 0x10 0x0000 XXXX GPIOx_ODT 0x14 0x0000 0000 GPIOx_SCR 0x18 0x0000 0000 GPIOx_WPR 0x1C 0x0000 0000 GPIOx_MUXL 0x20 0x0000 0000 GPIOx_MUXH 0x24 0x0000 0000 GPIOx_CLR 0x28 0x0000 0000 GPIOx_HDRV 0x3C 0x0000 0000 6 3 1 GPIO configuration register GPIOx_CFGR x A H Address offset 0x00 Reset values 0xa8000000 for port A 0x0000 0280 for por...

Page 135: ...et value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit 15 0 IDT 0xXXXX ro GPIOx input data Indicates the input status of I O port Each bit corresponds to an I O 6 3 6 GPIO output register GPIOx_IDH x A H Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit 15 0 ODT 0x0000 rw GPIOx output data Each bit represents an I...

Page 136: ...w write 1 write 0 write 1 read Note that the value of WPEN bit cannot be modified during this period Bit 15 0 WPEN 0x0000 rw Write protect enable Each bit corresponds to an I O port 0 No effect 1 Write protect 6 3 9 GPIO multiplexed function low register GPIOx_MUXL x A H Address offset 0x20 Reset value 0x00000000 Bit Register Reset value Type Description Bit 4y 3 4y MUXLy 0x0 rw Multiplexed functi...

Page 137: ...ter GPIOx_CLR x A H Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit 15 0 IOCB 0x0000 wo GPIOx clear bit The corresponding ODT register bit is cleared by writing 1 to these bits Otherwise the corresponding ODT register bit remains unchanged which acts as ODT register bit operations 0 No action to the corresponding ODT bits 1 Clear the correspon...

Page 138: ...0x0 rw XMC address mapping swap 00 No XMC address mapping swap 01 SDRAM addresses are mapped at 0x6000 0000 and 0x7000 0000 NOR PSRAM SRAM NAND2 memory addresses are mapped at 0xC000 00000 and 0xD000 0000 10 QSPI2 memory addresses are mapped at 0x8000 0000 NAND3 memory is mapped at 0xB000 0000 11 SDRAM memory addresses are mapped at 0x6000 0000 and 0x7000 0000 NOR PSRAM SRAM NAND2 memory addresses...

Page 139: ...Bit 22 0 Reserved 0x00000X resd Kept at its default value 7 2 3 SCFG external interrupt configuration register1 SCFG_ EXINTC1 Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit 15 12 EXINT3 0x0000 rw EXINT3 input source configuration These bits are used to select the input source for the EXINT3 external interrupt 0000 GPIOA pin3 0001 GPIOB pin3 0...

Page 140: ... SCFG external interrupt configuration register2 SCFG_ EXINTC2 Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit 15 12 EXINT7 0x0000 rw EXINT7 input source configuration These bits are used to select the input source for the EXINT7 external interrupt 0000 GPIOA pin7 0001 GPIOB pin7 0010 GPIOC pin7 0011 GPIOD pin7 0100 GPIOE pin7 0101 GPIOF pin7 ...

Page 141: ... 0010 GPIOC pin4 0011 GPIOD pin4 0100 GPIOE pin4 0101 GPIOF pin4 0110 GPIOG pin4 0111 GPIOH pin4 Others Reserved 7 2 5 SCFG external interrupt configuration register3 SCFG_ EXINTC3 Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit 15 12 EXINT11 0x0000 rw EXINT11 input source configuration These bits are used to select the input source for the EX...

Page 142: ...ource configuration These bits are used to select the input source for the EXINT8 external interrupt 0000 GPIOA pin8 0001 GPIOB pin8 0010 GPIOC pin8 0011 GPIOD pin8 0100 GPIOE pin8 0101 GPIOF pin8 0110 GPIOG pin8 0111 GPIOH pin8 Others Reserved 7 2 6 SCFG external interrupt configuration register4 SCFG_ EXINTC4 Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its de...

Page 143: ...13 0x0000 rw EXINT13 input source configuration These bits are used to select the input source for the EXINT13 external interrupt 0000 GPIOA pin13 0001 GPIOB pin13 0010 GPIOC pin13 0011 GPIOD pin13 0100 GPIOE pin13 0101 GPIOF pin13 0110 GPIOG pin13 0111 GPIOH pin13 Others Reserved Bit 3 0 EXINT12 0x0000 rw EXINT12 input source configuration These bits are used to select the input source for the EX...

Page 144: ...this bit is set the control bits of GPIOx_OTYPER GPIOx_HDRV become invalid Bit 7 PD14_UH 0x0 rw PD14 Ultra high sourcing sinking strength This bit is written by software to control the PD14 PAD sourcing sinking strength 0 Not active 1 Corresponding GPIO is switched to ultra high sourcing sinking strength When this bit is set the control bits of GPIOx_OTYPER GPIOx_HDRV become invalid Bit 6 PD13_UH ...

Page 145: ...trength 0 Not active 1 Corresponding GPIO is switched to ultra high sourcing sinking strength When this bit is set the control bits of GPIOx_OTYPER GPIOx_HDRV become invalid Bit 0 PB3_UH 0x0 rw PB3 Ultra high sourcing sinking strength This bit is written by software to control the PB3 PAD sourcing sinking strength 0 Not active 1 Corresponding GPIO is switched to ultra high sourcing sinking strengt...

Page 146: ...nd configuration procedure With up to 23 interrupt lines EXINT_LINE 22 0 EXINT can detect not only GPIO external interrupt sources but also seven internal sources such as PVM output ERTC alarm events and time stamp events ERTC wakeup events OTGFS1 OTGFS2 events and Ethernet wakeup events through edge detection mechanism where GPIO interrupt sources can be selected with IOMUX_EXINTCx register It sh...

Page 147: ... Bit Register Reset value Type Description Bit 31 23 Reserved 0x000 resd Forced to 0 by hardware Bit 22 0 INTENx 0x00000 rw Interrupt enable or disable on line x 0 Interrupt request is disabled 1 Interrupt request is enabled Note Bit 19 is applied to only AT32F434 437A and is reserved otherwise 8 3 2 Event enable register EXINT_EVTEN Bit Register Reset value Type Description Bit 31 23 Reserved 0x0...

Page 148: ...on line x If the corresponding bit in EXINT_INTEN register is 1 the software writes to this bit The hardware sets the corresponding bit in the EXINT_INTSTS automatically to generate an interrupt If the corresponding bit in the EXINT_EVTEN register is 1 the software writes to this bit The hardware generates an event on the corresponding interrupt line automatically 0 Default value 1 Software trigge...

Page 149: ...EQ and HGRANT of AHB master interface are not supported Support 7 channels Peripheral to memory memory to peripheral and memory to memory transfers Support hardware handshake Support 8 bit 16 bit and 32 bit data transfers Programmable amount of data to be transferred up to 65535 Support flexible mapping Figure 9 1 DMA block diagram Note The number of DMA peripherals in Figure 9 1 may decrease depe...

Page 150: ...xample channel 1 has priority over channel 2 Data transfer direction DTD Memory to peripheral M2P peripheral to memory P2M Address incremented mode PINCM MINCM In incremented mode the subsequent transfer address is the previous address plus transfer width PWIDTH MWIDTH Circular mode LM In circular mode the contents in the DMA_CxDTCNT register is automatically reloaded with the initially programmed...

Page 151: ... a single transfer based on the master controller priority Figure 9 2 Re arbitrate after request acknowledge dma_req dma_ack One single transfer Antother single transfer Re arbitrate Re arbitrate 9 3 4 Programmable data transfer width Transfer width of the source data and destination data is programmable through the PWIDTH and MWIDTH bits in the DMA_CxCTRL register When PWIDTH is not equal to MWID...

Page 152: ...r Each channel has its specific interrupt flag clear and enable bits as shown in the table below Table 9 2 DMA interrupt requests Interrupt event Event flag bit Clear control bit Enable control bit Half transfer HDTF HDTFC HDTIEN Transfer completed FDTF FDTFC FDTIEN Transfer error DTERRF DTERRFC DTERRIEN 9 4 DMA multiplexer DMAMUX DMAMUX manages DMA requests acknowledge between peripherals and DMA...

Page 153: ...nchronous mode the SYNCSEL bit in the DMA_MUXSxCTRL register is used to select synchronized input The selected DMA request input will be transferred to chx_mux_req 7 0 as soon as a valid edge of the synchronized input is detected by the SYNCPOL 1 0 in the DMA_MUXSxCTRL register In addition when the EVTGEN bit is set in the DMA_MUXCxCTRL register the programmable request counter REQCNT is used to g...

Page 154: ..._CH4 77 TMR5_TRIG 109 reserved 14 SPI3_RX 46 TMR1_OVERFLOW 78 reserved 110 I2S2_EXT_RX 15 SPI3_TX 47 TMR1_TRIG 79 reserved 111 I2S2_EXT_TX 16 I2C1_RX 48 TMR1_HALL 80 reserved 112 I2S3_EXT_RX 17 I2C1_TX 49 TMR8_CH1 81 reserved 113 I2S3_EXT_TX 18 I2C2_RX 50 TMR8_CH2 82 reserved 114 USART6_RX 19 I2C2_TX 51 TMR8_CH3 83 reserved 115 USART6_TX 20 I2C3_RX 52 TMR8_CH4 84 reserved 116 UART7_RX 21 I2C3_TX 5...

Page 155: ...9 4 2 DMAMUX overflow interrupts During DMAMUX request generation when a new trigger input occurs before the GREQCNT underflows the TRGOVFx bit will be set in the DMA_MUXGSTS register It is cleared by setting TRGOVFCx 1 in the DMA_MUXGCLR register An interrupt will be generated if the interrupt enable bit TRGOVIEN is set in the DMA_MUXGxCTRL register In DMAMUX synchronous mode when a new synchroni...

Page 156: ... DMA_STS 0x00 0x0000 0000 DMA_CLR 0x04 0x0000 0000 DMA_C1CTRL 0x08 0x0000 0000 DMA_C1DTCNT 0x0c 0x0000 0000 DMA_C1PADDR 0x10 0x0000 0000 DMA_C1MADDR 0x14 0x0000 0000 DMA_C2CTRL 0x1c 0x0000 0000 DMA_C2DTCNT 0x20 0x0000 0000 DMA_C2PADDR 0x24 0x0000 0000 DMA_C2MADDR 0x28 0x0000 0000 DMA_C3CTRL 0x30 0x0000 0000 DMA_C3DTCNT 0x34 0x0000 0000 DMA_C3PADDR 0x38 0x0000 0000 DMA_C3MADDR 0x3c 0x0000 0000 DMA_...

Page 157: ...MUXGSTS 0x138 0x0000 0000 DMA_MUXGCLR 0x13c 0x0000 0000 9 5 1 DMA interrupt status register DMA_STS Access 0 wait state accessible by bytes half words or words Bit Register Reset value Type Description 31 28 Reserved 0x0 resd Kept at its default value Bit 27 DTERRF7 0x0 ro Channel 7 data transfer error event flag 0 No transfer error occurred 1 Transfer error occurred Bit 26 HDTF7 0x0 ro Channel7 h...

Page 158: ...fer error event flag 0 No transfer error occurred 1 Transfer error occurred Bit 14 HDTF4 0x0 ro Channel 4 half transfer event flag 0 No half transfer event occurred 1 Half transfer event occurred Bit 13 FDTF4 0x0 ro Channel 4 transfer complete event flag 0 No transfer complete event occurred 1 Transfer complete event occurred Bit 12 GF4 0x0 ro Channel 4 global event flag 0 No transfer error half t...

Page 159: ...Register Reset value Type Description 31 28 Reserved 0x0 resd Kept at its default value Bit 27 DTERRFC7 0x0 rw1c Channel 7 data transfer error flag clear 0 No effect 1 Clear the DTERRF flag in the DMA_STS register Bit 26 HDTFC7 0x0 rw1c Channel 7 half transfer flag clear 0 No effect 1 Clear the HDTF7 flag in the DMA_STS register Bit 25 FDTFC7 0x0 rw1c Channel 7 transfer complete flag clear 0 No ef...

Page 160: ...he DMA_STS register Bit 10 HDTFC3 0x0 rw1c Channel 7 half transfer flag clear 0 No effect 1 Clear the HDTF7 flag in the DMA_STS register Bit 9 FDTFC3 0x0 rw1c Channel 3 transfer complete flag clear 0 No effect 1 Clear the FDTF3 flag in the DMA_STS register Bit 8 GFC3 0x0 rw1c Channel 3 global interrupt flag clear 0 No effect 1 Clear the DTERRF3 HDTF3 FDTF3 and GF3 flag in the DMA_STS register Bit ...

Page 161: ...1 Very high Bit 11 10 MWIDTH 0x0 rw Memory data bit width 00 8 bits 01 16 bits 10 32 bits 11 Reserved Bit 9 8 PWIDTH 0x0 rw Peripheral data bit width 00 8 bits 01 16 bits 10 32 bits 1 Reserved Bit 7 MINCM 0x0 rw Memory address increment mode 0 Disabled 1 Enabled Bit 6 PINCM 0x0 rw Peripheral address increment mode 0 Disabled 1 Enabled Bit 5 LM 0x0 rw Circular mode 0 Disabled 1 Enabled Bit 4 DTD 0x...

Page 162: ...ess of peripheral data register is the source or destination of data transfer Note The register can only be written when the CHEN bit in the corresponding channel is set 0 9 5 6 DMA channel x memory address register DMA_CxMADDR x 1 7 Access 0 wait state accessible by bytes half words or words Bit Register Reset value Type Description Bit 31 0 MADDR 0x0000 0000 rw Memory base address Memory address...

Page 163: ...e 0 Event generation is disabled 1 Event generation is enabled Bit 8 SYNCOVIEN 0x0 Synchronization overrun interrupt enable 0 Interrupt disabled 1 Interrupt enabled Bit 7 Reserved 0x0 resd Kept at its default value Bit 6 0 REQSEL 0x00 DMA request select Select DMA request Refer to DMAMUX table for more information 9 5 9 DMAMUX generator x control register DMA_MUXGxCTRL x 1 4 Access 0 wait state ac...

Page 164: ...e Bit 7 0 SYNCOVF 0x00 ro Synchronization overrun interrupt flag When the DMA request count is less than REQCNT this bit is set while a new synchronization event occurs 9 5 11 DMAMUX channel interrupt clear flag register DMA_MUXSYNCCLR Access 0 wait state accessible by bytes half words or words Bit Register Reset value Type Description Bit 31 8 Reserved 0x0000 00 resd Kept at its default value Bit...

Page 165: ...gister DMA_MUXGCLR Access 0 wait state accessible by bytes half words or words Bit Register Reset value Type Description Bit Register Reset value Type Description Bit 3 0 TRGOVFC 0x00 rw1c Trigger overrun interrupt flag clear Writing 1 to the corresponding bit can clear the TRGOVF flag in the DMA_MUXGSTS register ...

Page 166: ...o CRC_DT register after each CRC reset 10 2CRC registers CRC_DT register can be accessed by bytes 8 bits half words 16 bits or words 32 bits Other registers have to be accessed by words 32 bits Table 10 1 CRC register map and reset value Register Offset Reset value CRC_DT 0x00 0xFFFF FFFF CRC_CDT 0x04 0x0000 0000 CRC_CTRL 0x08 0x0000 0000 CRC_IDT 0x10 0xFFFF FFFF 10 2 1 Data register CRC_DT Bit Re...

Page 167: ...resd Kept at its default value Bit 0 RST 0x0 rw Reset CRC calculation unit Set by software Cleared by hardware To reset CRC calculation unit the data register is set as 0xFFFF FFFF 0 No effect 1 Reset 10 2 4 Initialization register CRC_IDT Bit Register Reset value Type Description Bit 31 0 IDT 0xFFFF FFFF rw Initialization data register When CRC reset is triggered by the RST bit in the CRC_CTRL re...

Page 168: ...l noise filter Support SMBus2 protocol PEC generation and verification Acknowledgement control for command and data ARP address resolution protocol Master capability Device capability SMBus reminder capability Timeout detection Idle detection PMBus 11 3I2C function overview I2 C bus consists of a data line SDA and clock line SCL It can achieve a maximum of 100 kHz speed in standard mode whereas up...

Page 169: ...terface switches from slave mode to master mode and returns to slave mode automatically at the end of data transfer Stop condition is triggered 2 Communication process Master mode communication 1 Start condition generation 2 Address transmission 3 Data Tx or Rx 4 Stop condition generation 5 End of communication Slave mode communication 1 Wait until the address is matched 2 Data Tx or Rx 3 Wait for...

Page 170: ...If the clock stretching capability is not supported by master then the STRETCH must be set in the I2C_CTRL register It should be noted that the clock stretching capability of I2C slave must be configured before the I2C peripherals are enabled Clock stretching capability enabled I2 C slave stretches the SCL clock in one of the following conditions Address reception When the address received by slav...

Page 171: ...time tSU DAT SCLH 7 0 SCL high SCLL 7 0 SCL low Note Timing configuration cannot be modified once the I2 C is enabled Figure 11 3 Setup and hold time It is possible to configure data hold time tHD DAT and data setup time tSU DAT freely by setting the DIV 7 0 SDAD 3 0 and SCLD 3 0 in the I2C_CLKCTRL register Data hold time tHD DAT refers to the duration from SCL falling edge to SDA output tHD DAT t...

Page 172: ...control communication flow It is mainly used for NACK transmission master reception mode STOP transmission master reception transmission modes RESTART generation master reception transmission modes ACK control slave mode SMBus PEC transmission reception master slave modes Generally the data transfer management counter by setting the CNT 7 0 in the I2C_CTRL2 is applicable to master mode It is disab...

Page 173: ...CRLD is set in the I2C_STS register and the slave will pull the SCL bus low between the 8th and 9th clock edges At this point the user can read the RXDT register and generate an ACK or NACK signal through the NACKEN bit in the I2C_CTRL2 register When an NACK signal is generated it indicates the end of communication When an ACK signal is generated the communication flow keeps going on At this point...

Page 174: ...ing 1 to the TXDT register and data is immediately moved to the shift register 3 TXDT register becomes empty TDIS 1 again 4 Writing 2 to the TXDT register TDIS is cleared 5 Repeat step 2 and 3 until the data in the CNT 7 0 is sent 6 If TCRLD 1 reload mode in the I2C_STS register the following two circumstances should be noted Remaining bytes N 255 write 255 to the CNT bit N N 255 TCRLD is cleared ...

Page 175: ...smission flow Master initialization I2C_STS_TDIS 1 No Set I2C_CTRL2_CNT N if N 255 CNT 0xFF N N 255 RLDEN 1 Configure slave address and GENSTART 1 I2C_STS_ACKFAIL 1 Yes Yes No Write I2C_TXDT_DT CNT Transmitted I2C_STS_TDC 1 No No Yes Yes ASTOPEN 0 I2C_STS_TCRLD 1 Yes No ASTOPEN 1 N 256 CNT N RLDEN 0 Yes CNT 0xFF N N 255 RLDEN 1 No Wait I2C_STS_STOPF 1 Set I2C_CLR_STOPC 1 I2C_CLR_ACKFAILC 1 Set I2C...

Page 176: ...ite Data2 EV4 I2C_STS_TDIS 1 write Data3 EV5 I2C_STS_TDIS 1 write DataN EV6 I2C_STS_STOPF 1 set I2C_CLR_STOPC 1 TDIS EV3 EV2 EV4 EV6 A DataN EV5 EV1 Initial setting Master receiver Figure 11 6 I2C master receive flow Master initialization I2C_STS_RDBF 1 Set I2C_CTRL2_CNT N if N 255 CNT 0xFF N N 255 RLDEN 1 Configure slave address and GENSTART 1 Yes No Read I2C_RXDT_DT CNT received I2C_STS_TDC 1 No...

Page 177: ...a special timing When READH10 1 the master sends data to the slave before read access to the slave as shown in the figure below Operating method When ASTOPEN 0 data is transferred from the master to the slave At the end of data transfer READH10 0 is asserted and then the master starts receiving data from the slave Figure 11 8 10 bit address read access when READH10 1 Data A Master to Slave Slave t...

Page 178: ...s SDIR 1 indicates that the slave is sending data The ADDR 6 0 bit of the I2C_STS register indicates what kind of address has been received which is particularly helpful in the case when the dual address mode is used and the address 2 mode mask bit is set Data transfer starts when the ADDRF is cleared by setting ADDRC 1 of the I2C_CLR register 5 Data transfer slave transmission clock stretching en...

Page 179: ...mpletion of all data transfer 4 Wait for the generation of a STOP condition Once received the STOPF is set in the I2C_STS register The STOPF can be cleared by writing 1 to the STOPC bit in the I2C_CLR register transfer ends In slave receive mode the slave byte control mode can be used for data reception This mode allows to control ACK NACK signals of each byte received This mode is typically avail...

Page 180: ...ion if STRETCH 1 write data to I2C_TXDT_DT Set I2C_STS_TDBE 1 and I2C_CLR_TDIS 1 Set I2C_CLR_STOPC 1 Figure 11 11 I2C slave transmission timing Address S r w A Data1 A SCL Stretch Data2 A DataN NA P Master to Slave Slave to Master S Start A Acknowledge P Stop I2C Slave transfer N bytes to I2C master EV1 I2C_STS1_ADDRF 1 set I2C_CLR_ADDRC 1 EV2 write Data1 I2C_STS1_TDIS 0 EV3 write Data2 I2C_STS1_T...

Page 181: ...XDT_DT Yes I2C_STS_STOPF 1 Yes No No Set I2C_CLR_STOPC 1 Figure 11 13 I2C slave receive timing Address S r w A Data1 A SCL Stretch Data2 A DataN A P Master to Slave Slave to Master S Start A Acknowledge P Stop I2C Slave receiver N bytes from I2C master EV1 I2C_STS_ADDRF 1 set I2C_CLR_ADDRC EV2 I2C_STS_RDBF 1 read Data1 EV3 I2C_STS_RDBF 1 read Data2 EV4 I2C_STS_RDBF 1 read DataN EV5 I2C_STS_STOPF 1...

Page 182: ...d be handled by software SMBus host notify protocol The slave device can send data to the master device through SMBus host notify protocol For example the slave can notify the host to implement ARP with this protocol Refer to SMBus 2 0 protocol for details on SMBus host notify protocol In host mode HADDREN 1 the I2 C interface is enabled to recognize the 0b0001000x default host address SMBus Alert...

Page 183: ... SCL is pulled low by a master device during the period from the ACK of the last byte to the 8th bit of the next byte a single byte It should be noted that both tLOW SEXT and tLOW MEXT only deal with the time when they set themselves low level excluding the time when they are pulled low by external sources In contrast both of these cases are considered in the calculation of tTIMEOU Table 11 3 SMBu...

Page 184: ... The SMBus is similar to the I2 C in terms of master communication flow 1 I2C clock initialization by setting the I2C_CLKCTRL register I2 C clock divider DIV 7 0 Data hold time tHD DAT SDAD 3 0 Data setup time tSU DAT SCLD 3 0 SCL high duration SCLH 7 0 SCL low duration SCLL 7 0 The register can be configured by means of Artery_I2C_Timing_Configuration tool 2 SMBus related initialization Select SM...

Page 185: ...mmediately moved to the shift register 3 TXDT register becomes empty TDIS 1 again 4 Writing 2 to the TXDT register TDIS is cleared 5 Repeat step 2 and 3 until the specified data N 1 is sent 6 The master will automatically transmit the Nth data that is PEC 9 Master receive 1 After the reception of data RDBF 1 read the RXDT register will clear the RDBF automatically 2 Repeat step 1 until the recepti...

Page 186: ...ECEN 1 I2C_CTRL2_PECTEN 1 Configure slave address GENSTART 1 I2C_STS_ACKFAIL 1 Wait I2C_STS_STOPF 1 Set I2C_CLR_STOPC 1 I2C_CLR_ACKFAILC 1 Yes Yes No Write I2C_TXDT_DT N Bytes Transmitted ASTOPEN 0 No Yes No ASTOPEN 1 Yes ASTOPEN 0 Set I2C_CTRL2_GENSTOP 1 Wait I2C_STS_STOPF 1 Set I2C_CLR_STOPC 1 Restart Configure CNT and slave address GENSTART 1 No Yes I2C_STS_TDC 1 Wait I2C_STS_STOPF 1 Set I2C_CL...

Page 187: ...2C_STS_TDIS 1 write Data1 EV3 I2C_STS_TDIS 1 write Data2 EV4 I2C_STS_TDIS 1 write Data3 EV5 I2C_STS_TDIS 1 write DataN EV6 I2C_STS_STOPF 1 set I2C_CLR_STOPC 1 TDIS EV3 EV2 EV4 EV6 A PEC EV5 EV1 DataN A Initial setting SMBus master receive flow Figure 11 16 SMBus master receive flow Master initialization I2C_STS_RDBF 1 Set I2C_CTRL2_CNT N 1 I2C_CTRL1_PECEN 1 I2C_CTRL2_PECTEN 1 Configure slave addre...

Page 188: ...ADDR1 register Enable address 1 by setting ADDR1EN 1 in the I2C_OADDR1 register 3 SMBus related initialization Select SMBus host device default address acknowledged 0b1100001x by setting DEVADDREN 1 Enable PEC calculation Set PECEN 1 in the I2C_CTRL1 register Set slave byte control mode Slave transmit disable byte control mode by setting SCTRL 0 in the I2C_CTRL1 register Slave receive enable byte ...

Page 189: ...r the STOPF is cleared by writing 1 to the STOPC transmission ends 6 Data transfer slave receive clock stretching enabled STRETCH 0 After address matching 1 I2C_RXDT register becomes empty the shift register becomes empty and RDBF 0 in the I2C_STS register 2 Upon the receipt of one byte data RDBF 1 and TCRLD 1 then the SCL is pulled low by the slave 3 The RDBF is cleared by read operation to the R...

Page 190: ..._STS_STOPF 1 Yes Yes No No Set I2C_STS_TDBE 1 and I2C_CLR_TDIS 1 Set I2C_CLR_STOPC 1 Figure 11 19 SMBus slave transmission timing Address S r w A Data1 A Data2 A P Master to Slave Slave to Master S Start A Acknowledge P Stop SMBus slave transmitter N bytes PEC EV1 I2C_STS_ADDRF 1 set I2C_CTRL2 CNT N 1 PECTEN 1 I2C_CLR_ADDRC 1 EV2 I2C_STS_TDIS write Data1 EV3 I2C_STS_TDIS write Data2 EV4 I2C_STS_TD...

Page 191: ...LD 1 Yes No I2C_STS_RDBF 1 No Read I2C_RXDT_DT Yes I2C_STS_STOPF 1 Yes No Set I2C_CLR_STOPC 1 Slave initialization I2C_CTRL1_PECEN 1 Yes Figure 11 21 SMBus slave receive timing Address S r w A Data1 A Data2 A P Master to Slave Slave to Master S Start A Acknowledge P Stop SMBus slave receiver N bytes PEC EV1 I2C_STS_ADDR 1 Set I2C_CTRL2 CNT N 1 PECTEN 1 and set I2C_CLR_ADDRC 1 EV2 I2C_STS_RDBF read...

Page 192: ...MAREN 1 1 Set the peripheral address DMA_CxPADDR I2C_RXDT address 2 Set the memory address DMA_CxMADDR memory address 3 The transmission directions set from peripheral to memory DTD 0 in the DMA_CHCTRL register 4 Configure the total number of bytes to be transferred in the DMA_CxDTCNT register 5 Configure other parameters such as priority memory data width peripheral data width interrupts etc in t...

Page 193: ...ill be released and go automatically back to slave mode Bus error BUSERR The SDA line during a data transfer must be kept in a stable state when the SCL is in high level The SDA can be changed only when the SCL signal becomes low otherwise a bus error may appear When the SCL is high SDA changes from 1 to 0 a misplaced START condition SDA changes from 0 to 1 a misplaced STOP condition Both of these...

Page 194: ...r TMOUT PEC error PECERR Overrun Underrun OUF Arbitration lost ARLOST Bus error BUSERR 11 6I2C debug mode When the microcontroller enters debug mode CortexTM M4 halted the SMBUS timeout either continues to work or stops depending on the I2Cx_SMBUS_TIMEOUT configuration bit in the DEBUG module 11 7I2C registers These peripheral registers must be accessed by words 32 bits Table 11 8 I2C register map...

Page 195: ...x Bit 18 Reserved 0x0 res Kept at its default value Bit 17 STRETCH 0x0 rw Clock stretching mode 0 Clock stretching mode enabled 1 Clock stretching mode disabled Note This feature is valid in slave mode only Bit 16 SCTRL 0x0 rw Slave receive data control 0 Slave receive data disabled 1 Slave receive data enabled Bit 15 DMAREN 0x0 rw DMA receive data request enable 0 DMA receive data request disable...

Page 196: ...n disabled 1 Transmission enabled Bit 25 ASTOPEN 0x0 rw Automatically send stop condition enable 0 Disabled Software sends STOP condition 1 Enabled Automatically send STOP condition Bit 24 RLDEN 0x0 rw Send data reload mode enable 0 Send data reload mode disable 1 Send data reload mode enabled Bit 23 16 CNT 7 0 0x00 rw Transmit data counter Bit 15 NACKEN 0x0 rw Not acknowledge enable 0 Acknowledge...

Page 197: ...addresses other than those reserved for I2C Bit 7 1 ADDR2 7 1 0x00 rw Own address 2 7 bit address mode Bit 0 Reserved 0x0 res Kept at its default value 11 7 5 Timing register I2C_CLKCTRL Bit Register Reset value Type Description Bit 31 28 DIVL 3 0 0x0 rw Low 4 bits of clock divider value Bit 27 24 DIVH 7 4 0x0 rw High 4 bits of clock divider value DIV DIVH 4 DIVL Bit 23 20 SCLD 3 0 0x0 rw SCL outp...

Page 198: ... detected this bit is automatically cleared Bit 14 Reserved 0x00 res Kept at its default value Bit 13 ALERTF 0x0 r SMBus alert flag SMBus host This bit indicates the reception of an alert signal ALERT pin changes from high to low 0 No alert signal received 1 Alert signal received Bit 12 TMOUT 0x0 r SMBus timeout flag 0 No timeout 1 Timeout Bit 11 PECERR 0x0 r PEC receive error flag 0 No PEC error ...

Page 199: ...s Transmit data buffer empty flag 0 I2C_TXDT not empty 1 I2C_TXDT empty This bit is only used to indicate the current status of the I2C_TXDT register The I2C_TXDT register can be cleared by writing 1 through software 11 7 8 Status clear register I2C_CLR Bit Register Reset value Type Description Bit 31 14 Reserved 0x00000 res Kept at its default value Bit 13 ALERTC 0x0 w Clear SMBus alert flag SMBu...

Page 200: ... 7 0 PECVAL 7 0 0x00 r PEC value 11 7 10Receive data register I2C_RXDT Bit Register Reset value Type Description Bit 31 8 Reserved 0x000000 res Kept at its default value Bit 7 0 DT 7 0 0x00 r Receive data register 11 7 11Transmit data register I2C_TXDT Bit Register Reset value Type Description Bit 31 8 Reserved 0x000000 res Kept at its default value Bit 7 0 DT 7 0 0x00 rw Transmit data register ...

Page 201: ...onous SmartCard protocol defined in ISO7816 3 standard and CTS RTS Clear To Send Request To Send hardware flow operation It also allows mutli processor communication and supports silent mode waken up by idle frames or ID matching to build up a USART network Meanwhile high speed communication is possible by using DMA Figure 12 1 USART block diagram USART interrupt control logic USART control logic ...

Page 202: ...Shared by transmission and reception up to 9 MBits s Programmable frame format Programmable data word length 7 bits 8 bits or 9 bits Programmable stop bits support 1 or 2 stop bits Programmable parity control transmitter with parity bit transmission capability and receiver with received data parity check capability Programmable DMA multi processor communication Programmable separate enable bits fo...

Page 203: ...oduction USART mode selector allows USART to work in different operation modes through software configuration so as to enable data exchanges between USART and peripherals with different communication protocols USART supports NRZ standard format Mark Space by default It also supports LIN Local Interconnection Network IrDA SIR Serial Infrared Asynchronous Smartcard protocol in ISO7816 3 standard RS ...

Page 204: ...n be asserted high after the guard time counter reaches the value programmed in the SCGT 7 0 bit The Smartcard is a single wire half duplex communication protocol The SCNACKEN bit is used to select whether to send NACK when a parity error occurs This is to indicate to the Smarcard that the data has not been correctly received Figure 12 3 Smartcard frame format Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 B...

Page 205: ...control frame2 5 RS485 mode This mode is enabled by setting RS485EN 1 The enable signal is output on the RTS pin The DEP bit is used to select the polarity of the DE signal The TSDT 4 0 bit is used to define the latency before the transmission of the start bit on the transmitter side while the TCDT 4 0 is used to define the latency before the TC flag is set following the stop bit at the end of the...

Page 206: ...irst edge of the clock depends on the CLKPHA bit 1 or 0 The LBCP bit 1 or 0 is used to select whether to output clock on the last data bit And the ISDIV 4 0 is used to select the required clock output frequency Figure 12 7 8 bit format USART synchronous mode Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop bit Start bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Start bit TX pin RX pin St...

Page 207: ...rity bit Data frame Idle frame Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Start bit Stop bit 8 bit word length DBN1 DBN0 00 Next Start bit Clock Start bit Next Data frame PEN 1 Parity bit Data frame Idle frame Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Start bit Stop bit 7 bit word length DBN1 DBN0 10 Next Start bit Clock Start bit Next Data frame PEN 1 Parity bit Data frame Idle frame The STO...

Page 208: ...ing DMA 1 Select a DMA channel Select a DMA channel from DMA channel map table described in DMA chapter 2 Configure the destination of DMA transfer Configure the USART_DT register address as the destination address bit of DMA transfer in the DMA control register Data will be sent to this address after transmit request is received by DMA 3 Configure the source of DMA transfer Configure the memory a...

Page 209: ... 16 equal parts to achieve oversampling so the data bit width should not be less than 16 PCLK periods that is the DIV value must be equal to or greater than 16 12 6 2 Configuration User can program the desired baud rate by setting different system clocks and writing different values into the USART_BAUDR register The calculation format is as follows TX RX 𝑏𝑎𝑢𝑑 𝑟𝑎𝑡𝑒 𝑓𝐶𝐾 DIV Where 𝑓𝐶𝐾 refers to the s...

Page 210: ...n the TX pin will be corrupted 2 After the TEN bit is enabled the USART will automatically send an idle frame 12 7 2 Transmitter configuration 1 USART enable Set the UEN bit 2 Full duplex half duplex configuration Refer to 12 2 Full duplex half duplex selector 3 Mode configuration Refer to 12 3 Mode selector 4 Frame format configuration Refer to 12 4 USART frame format and configuration 5 Interrup...

Page 211: ...l is selected the control signal is output on the RTS pin During data reception the USART receiver will detect whether there are errors to occur including framing error overrun error parity check error or noise error depending on software configuration and whether there are interrupts to generate using the interrupt enable bits 12 8 2 Receiver configuration Configuration procedure 1 USART enable U...

Page 212: ...s set The data in the receive data buffer is not lost The previous data is still available when the USART_DT register is read The content in the receive shift register is overwritten Afterwards any data received will be lost An interrupt is generated if the RDBFIEN is set or both ERRIEN and DMAREN are set The ROERR bit is cleared by reading the USART_STS register and then USART_DT register in orde...

Page 213: ...same time as the RDBF bit The invalid data is transferred from the receive shift register to the receive data buffer No interrupt is generated in non DMA mode However since the NERR bit is set at the same time as the RDBF bit the RDBF bit will generate an interrupt In DMA mode an interrupt will be issued if the ERRIEN is set The NERR bit is cleared by read access to USART_STS register followed by ...

Page 214: ...ource inside the USART in real time and the generation of interrupts according to the programmed interrupt control bits Table 12 4 shows the USART interrupt source and interrupt enable control bit An interrupt will be generated over an event when the corresponding interrupt enable bit is set Table 12 4 USART interrupt request Interrupt event Event flag Enable bit Transmit data register empty TDBE ...

Page 215: ...nd request signal in hardware flow control mode 12 12 USART registers These peripheral registers must be accessed by words 32 bits Table 12 5 USART register map and reset value Register Offset Reset value USART_STS 0x00 0x0000 00C0 USART_DT 0x04 0x0000 0000 USART_BAUDR 0x08 0x0000 0000 USART_CTRL1 0x0C 0x0000 0000 USART_CTRL2 0x10 0x0000 0000 USART_CTRL3 0x14 0x0000 0000 USART_GTP 0x18 0x0000 0000...

Page 216: ...flow error This bit is set by hardware when the data is received while the RDNE is still set It is cleared by software Read USART_STS register followed by a USART_DT read operation 0 No overflow error 1 Overflow error is detected Note When this bit is set the DT register content will not be lost but the subsequent data will be overwritten Bit 2 NERR 0x0 ro Noise error This bit is set by hardware w...

Page 217: ...of 1 16 baud rate Bit 20 16 TCDT 0x00 rw transmit complete delay time In RS485 mode a period of time delay is needed before the last data transfer is complete even if the last STOP bit has been transferred This time duration allows the transfer direction of the external receiver transmitter to switch back to receive This time depends on the TCDT value in unit of 1 16 baud rate Bit 15 14 Reserved 0...

Page 218: ...ute mode it is cleared by hardware after wake up When address mismatches this bit is set by hardware to enter mute mode again 0 Receiver is in active mode 1 Receiver is in mute mode Bit 0 SBF 0x0 rw Send brake frame This bit is used to send a brake frame It can be set or cleared by software Generally speaking it is set by software and cleared by hardware at the end of brake frame transmission 0 No...

Page 219: ...frame Bit 4 IDBN 0x0 rw Identification bit num This bit is used to select ID bit number 0 4 bit 1 Data bit 1 bit Note When this bit is set in 7 8 or 8 bit data mode the ID bit number is the lower 6 7 or 8 bit respectively Bit 3 0 IDL 0x0 rw USART identification This field holds the lower four bits of USART ID It is configurable Note These three bits CLKPOL CLKPHA and LBCP should not be changed whi...

Page 220: ...IrDA enable 0 IrDA is disabled 1 IrDA is enabled Bit 0 ERRIEN 0x0 rw Error interrupt enable An interrupt is generated when a framing error overflow error or noise error occurs 0 Error interrupt is disabled 1 Error interrupt is enabled 12 12 7Guard time and divider register USART_GDIV Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Forced 0 by hardware Bit 15 8 SCGT 0x00 rw...

Page 221: ...s SPI block diagram Figure 13 1 SPI block diagram SPI_SCK controller SPI_STS BF ROE RR MME RR CCE RR TUER R ACS TDBE RDBF Communication controller CS controller SWCSEN SWCSIL SLBEN SLBTD ORA MDIV3EN MDIV 3 0 CLKPOL CLKPHA MSTEN Transmitter logic Transmission CRC unit CCEN NTC LTF SPIEN FBN TIEN MOSI MISO SCK CS Full Duplex Ha rf duplex selector Receiver logic Receipt CRC unit Receive transmit date...

Page 222: ... wire unidirectional full duplex mode and SPI IO connection The SPI operates in two wire unidirectional full duplex mode when the SLBEN bit and the ORA bit is both 0 In this case the SPI supports data transmission and reception at the same time IO connection is as follows Figure 13 2 SPI two wire unidirectional full duplex connection SPI master SCK MISO MOSI CS SPI slave SCK MISO MOSI CS In either...

Page 223: ...o need to check any flag before disabling the SPI However it is required to wait until the BF becomes 0 before entering power saving mode Figure 13 5 shows single wire bidirectional half duplex mode and SPI IO connection When the SLBEN is set the SPI operates in single wire bidirectional half duplex mode In this case the SPI supports data reception and transmission alternately In master mode the M...

Page 224: ...re In master mode with CS being as an output HWCSOE 1 SWCSEN 0 the CS hardware control is enabled If the SPI is enabled low level is output on the CS pin The CS signal is then released after the SPI is disabled and the transmission is complete In master mode with CS being as an input HWCSOE 0 SWCSEN 0 the CS hardware control is enabled At this point the SPI is automatically disabled by hardware an...

Page 225: ...on and configuration procedure of the SPI are described as follows CRC configuration procedure CRC calculation polynomial is configured by setting the SPI_CPOLY register CRC enable The CRC calculation is enabled by setting the CCEN bit This operation will reset the SPI_RCRC and SPI_TCRC registers Select if or when the NTC bit is set depending on DMA or CPU data register See the following descripti...

Page 226: ... for the current SPI from DMA flexible request map table described in DMA chapter Configure the destination of DMA transfer Configure the memory address as the destination of DMA transfer in the DMA control register Data will be loaded from the SPI_DT register to the programmed destination after reception request is received by DMA Configure the source of DMA transfer Configure the SPI_DT register...

Page 227: ... are as follows Transmitter configuration procedure Configure full duplex half duplex selector Configure chip select controller Configure SPI_SCK controller Configure CRC if necessary Configure DMA transfer if necessary If the DMA transfer mode is not used the software will check whether to enable transmit data interrupt TDBEIE 1 through the TDBE bit Configure frame format select MSB LSB mode with...

Page 228: ... timings Full duplex communication master mode Configured as follows MSTEN 1 Master enable SLBEN 0 Full duplex mode CLKPOL 0 CLKPHA 0 SCK idle output low use the first edge for sampling FBN 0 8 bit frame Master transmit MOSI 0xaa 0xcc 0xaa Slave transmit MISO 0xcc 0xaa 0xcc Figure 13 6 Master full duplex communications SCK MISO TDBE flag BF flag CS MOSI RDBF flag 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 ...

Page 229: ... Figure 13 8 Master half duplex transmit SCK BF flag CS MOSI 1 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 TDBE flag Drive Transmit buffer empty and software can write data Half duplex communication slave receive Configured as follows MSTEN 0 Slave enable SLBEN 1 Single line bidirectional mode SLBTD 0 Receive mode CLKPOL 0 CLKPHA 0 SCK idle output low use the first edge for sampling FBN 0 8 bit ...

Page 230: ... 0 0 1 1 1 1 0 0 0 0 0 0 0 BF flag remains low RDBF flag Sampling Software needs to read the received data 13 2 11TI mode The SPI interface supports TI mode The TIEN bit can be set to enable SPI TI mode In TI mode a bit of different is present between continuous and discontinuous communication timings When the to be transmitted data is written before the rising SCK edge corresponding to the last d...

Page 231: ...SPI interrupts RDBF RDBFIE TDBE TDBEIE ROERR MMERR CCERR ERRIE SPI interrupt 13 2 13IO pin control Usually the SPI is connected to external devices through four pins MISO Master In Slave Out The pin receives data in master mode and transmits data in slave mode MOSI Master Out Slave In The pin transmits data in master mode and receives data in slave mode SCK SPI communication clock The pin serves a...

Page 232: ...ts half duplex However it can work with two additional instantiated I2 S modules I2 S2EXT and I2 S3EXT to achieve full duplex mode In other words combining the I2 S2 with the I2 S2EXT enables the I2 S2 to support full duplex mode This is true for the I2 S3 through the combination of the I2 S3 with the I2 S3EXT Refer to I2 S full duplex section for more information Figure 13 16 I2S block diagram I2...

Page 233: ...2 S I2 SxEXT I2Sx_SCK I2Sx_WS SPIx_MOSI I2Sx_SD in out I2Sx_SDext in out I2 Sx can be used as master where x should be 2 or 3 In half duplex mode only I2 Sx can output SCK and WS In full duplex mode only I2 Sx can output SCK and WS I2 SxEXT is only used for full duplex mode and I2 SxEXT only for slave mode Both the I2 Sx and I2 SxEXT can be configured as transmit or receive mode 13 3 3 Operating m...

Page 234: ...ter CK SD WS I2S slave CK SD WS Master device transmission Set the I2SMSEL bit and OPERSEL 1 0 10 the I2S will work in master device transmission mode Figure 13 20 I2S master device transmission I2S master CK SD WS I2S slave CK SD WS Master device reception Set the I2SMSEL bit and OPERSEL 1 0 11 the I2 S will work in master device reception mode Figure 13 21 I2S master device reception I2S master ...

Page 235: ...ansfer is 1 Philips standard PCM standard or MSB aligned standard 16 bit data and 32 bit channel The data bit is different from the channel bit Each channel requires one read write operation from to the SPI_DT register and the number of DMA transfer is 1 The first 16 bits MSB are the significant bits and the 16 bit LSB is forced to 0 by hardware Philips standard PCM standard or MSB aligned standar...

Page 236: ...munication clock When the main clock is not needed the prescaler of the CK is determined by I2SDIV and I2SODD shown in Figure 13 13 Figure 13 22 CK MCK source in master mode Divided by 2xI2SDIV 9 0 I 2SODD Divided by 8 Divided by 4 SCLK MCK CK I2SMCLKOE Divided by 2xI2SDIV 9 0 I 2SODD Divided by 2xI2SDIV 9 0 I 2SODD I2SCBN I2SCBN I2SMCLKOE 1 0 Apart from the above mentioned configuration the follo...

Page 237: ...1 36 100 No 44100 35 1 44014 08 0 19 17 1 44642 86 1 23 100 No 32000 49 0 31887 76 0 35 24 1 31887 76 0 35 100 No 22050 71 0 22007 04 0 19 35 1 22007 04 0 19 100 No 16000 97 1 16025 64 0 16 49 0 15943 88 0 35 100 No 11025 141 1 11042 4 0 16 71 0 11003 52 0 19 100 No 8000 195 1 7992 327 0 10 97 1 8012 821 0 16 100 Yes 96000 2 0 97656 25 1 73 2 0 97656 25 1 73 100 Yes 48000 4 0 48828 13 1 73 4 0 488...

Page 238: ...e the source of DMA transfer Configure the SPI_DT register address as the source of DMA transfer in the DMA control register Data will be loaded from the SPI_DT register to the programmed destination after reception request is received by DMA Configure the total number of bytes to be transferred in the DMA control register Configure the total number of bytes to be transferred in the DMA control re...

Page 239: ... Configure operation mode selector Configure audio protocol selector Configure I2S_SCK controller Configure DMA transfer if necessary Set the I2SEN bit to enable I2 S Follow above steps to configure the I2 SxEXT For I2 S full duplex mode 13 3 8 I2S communication timings I2S can address four different audio standards Philips standard the most significant byte left aligned and the least significant ...

Page 240: ...als The I2 S shares some pins with the SPI described as follows SD Serial data mapped on the MOSI pin for bidirectional data transmission and reception WS Word select mapped on the CS pin for data control signal output in master mode and input in slave mode CK Communication clock mapped on the SCK pin as clock signal output in master mode and input in slave mode MCLK Master clock mapped independen...

Page 241: ...e only mode 1 Transmit only mode Bit 13 CCEN 0x0 rw RC calculation enable 0 Disabled 1 Enabled Bit 12 NTC 0x0 rw Transmit CRC next When this bit is set it indicates that the next data transferred is CRC value 0 Next transmitted data is the normal value 1 Next transmitted data is CRC value Bit 11 FBN 0x0 rw Frame bit num This bit is used to configure the number of data frame bit for transmission re...

Page 242: ... 0 Data capture starts from the first clock edge 1 Data capture starts from the second clock edge Note The SPI_CTRL1 register must be 0 in I2 S mode 13 4 2 SPI control register2 SPI_CTRL2 Bit Register Reset value Type Description Bit 15 10 Reserved 0x00 resd Forced 0 by hardware Bit 9 MDIV3EN 0x0 rw Master clock frequency divided by 3 enable 0 Disabled 1 Enabled Note When this bit is set the MDIV ...

Page 243: ...7 BF 0x0 ro Busy flag 0 SPI is not busy 1 SPI is busy Bit 6 ROERR 0x0 ro Receiver overflow error 0 No overflow error 1 Overflow error occurs Bit 5 MMERR 0x0 ro Master mode error This bit is set by hardware and cleared by software read write access to the SPI_STS register followed by write operation to the SPI_CTRL1 register 0 No mode error 1 Mode error occurs Bit 4 CCERR 0x0 rw0c CRC error Set by ...

Page 244: ... the 8 bit LSB 7 0 are calculated based on CRC8 standard when 16 bit data bit is selected follow CRC16 standard Note This register is only used in SPI mode 13 4 7 SPITxCRC register SPI_TCRC Bit Register Reset value Type Description Bit 15 0 TCRC 0x0000 ro Transmit CRC When CRC calculation is enabled this register contains the CRC value computed based on the transmitted data This register is reset ...

Page 245: ...ngth 01 24 bit data length 10 32 bit data length 11 Not allowed Bit 0 I2SCBN 0x0 rw I2 S channel bit num This bit can be configured only when the I2 S is set to 16 bit data otherwise it is fixed to 32 bit by hardware 0 16 bit wide 1 32 bit wide 13 4 9 SPI_I2S prescaler register SPI_I2SCLKP Bit Register Reset value Type Description Bit 15 12 Reserved 0x0 resd Forced 0 by hardware Bit 9 I2SMCLKOE 0x...

Page 246: ...Down Up Down X 1 65535 O 4 O O X TMR3 TMR4 16 Up Down Up Down X 1 65535 O 4 O O X TMR9 TMR12 16 Up X 1 65535 X 2 O X X TMR10 TMR11 TMR13 TMR14 16 Up X 1 65535 X 1 X X X Basic timer TMR6 TMR7 16 Up X 1 65535 O X X X X Timer type Timer Counter bit Count mode PWM output Single pulse output Complementary output Dead time Encoder interface connection Interfacing with hall sensors Linkage peripheral Adv...

Page 247: ...3 2Counting mode The basic timer only supports upcounting mode and it has an internal 16 bit counter The TMRx_PR register is used to set the counting period The The value in the TMRx_PR is immediately moved to the shadow register by default When the periodic buffer is enabled PRBEN 1 the value in the TMRx_PR register is transferred to the shadow register only at an overflow event The TMRx_DIV regi...

Page 248: ...unter counts from 0 to the value programmed in the TMRx_PR register restarts from 0 and generates a counter overflow event with the OVFIF bit being set to 1 If the overflow event is disabled the counter is no longer reloaded with the preload value and period value at a counter overflow event otherwise the counter is updated with the preload value and period value at an overflow event Figure 14 4 O...

Page 249: ... TMR6 and TMR7 registers These peripheral registers must be accessed by word 32 bits In Table 14 2 all the TMRx registers are mapped to a 16 bit addressable space Table 14 2 TMR6 and TMR7 register table and reset value Register Offset Reset value TMRx_CTRL1 0x00 0x0000 TMRx_CTRL2 0x04 0x0000 TMRx_IDEN 0x0C 0x0000 TMRx_ISTS 0x10 0x0000 TMRx_SWEVT 0x14 0x0000 TMRx_CVAL 0x24 0x0000 TMRx_DIV 0x28 0x00...

Page 250: ...nerated by any of the following events Counter overflow Setting the OVFSWTR bit Overflow event generated from the slave controller 1 OEV event is disabled If the OVFSWTR bit is set or a hardware reset is generated from the slave controller the counter and the prescaler are reinitialized Note This bit is set and cleared by software Bit 0 TMREN 0x0 rw TMR enable 0 Disabled 1 Enabled 14 1 4 2 TMR6 an...

Page 251: ...it Register Reset value Type Description Bit 15 1 Reserved 0x0000 resd Kept at its default value Bit 0 OVFSWTR 0x0 rw0c Overflow event triggered by software An overflow event is trigged by software 0 No effect 1 Generate an overflow event by software write operation 14 1 4 6 TMR6 and TMR7 counter value TMRx_CVAL Bit Register Reset value Type Description Bit 15 0 CVAL 0x0000 rw Counter value 14 1 4...

Page 252: ...DC TMRx_CH4 TMRx_CH3 TMRx_CH2 TMRx_CH1 TMRX_EXT Polarity selection edge detector prescaler Reset mode Encoder interface TMRx_DIV CNT counter CH4 edge detector C4DT CH4 filter CH3 edge detector CH3 filter C4IFP4 C4IFP3 C4IRAW C3IFP4 C3IFP3 C3IRAW CH2 edge detector CH2 filter C2IFP2 C2IFP1 C2IRAW C1IFP2 CH1 edge detector CH1 filter C1IFP1 C1IRAW STCI STCI STCI STCI C4IN C3IN DIV C3IN C2IN DIV C2IN C...

Page 253: ...ounter clock can be provided by two external clock sources namely TRGIN and EXT signals SMSEL 3 b111 External clock mode A is selected Select an external clock source TRGIN signal by setting the STIS 2 0 bit to drive the counter to start counting The external clock sources include C1INC STIS 3 b100 channel 1 rising edge and falling edge C1IFP1 STIS 3 b101 channel 1 signal with filtering and polari...

Page 254: ...t counting frequency through the DIV 15 0 bit in TMRx_DIV register Set counting period through the PR 15 0 bit in TMRx_PR register Enable counter through the TMREN in TMRx_CTRL1 register Figure 14 10 Block diagram of external clock mode A TMRx_EXT ESF filter EXT C1INC C1IFP1 C2IPF2 TMRx_CH2 C2DF C2P C2CP filter edge dector TMRx_CH1 C1DF C1P C1CP filter edge dector STIS External clock mode A enable...

Page 255: ...only when the next overflow event occurs The internal trigger input is configured as follows Set the TMRx_PR register to set the counting period Set the TMRx_DIV register to set the counting frequency Set the TWCMSEL 1 0 bit in the TMRx_CTRL1 register to set the count mode Set the STIS 2 0 bit range 3 b000 3 b011 in the TMRx_STCTRL register and select internal trigger Set SMSEL 2 0 3 b111 in the T...

Page 256: ...ent source By default counter overflow underflow setting OVFSWTR bit and the reset signal generated by the slave timer controller in reset mode trigger the generation of an overflow event When the OVFS bit is set only counter overflow underflow triggers an overflow event Setting the TMREN bit TMREN 1 enables the timer to start counting Base on synchronization logic however the actual enable signal...

Page 257: ... down counting mode In this mode the counter counts up down alternatively When the counter counts from the value programmed in the TMRx_PR register down to 1 an underflow event is generated and then restarts counting from 0 When the counter counts from 0 to the value of the TMRx_PR register 1 an overflow event is generated and then restarts counting from the value of the TMRx_PR register The OWCDI...

Page 258: ...IFP2 Encoder mode B SMSEL 3 b010 The counter counts on the selected C2IFP2 edge rising and falling edges and the counting direction is dependent on the edge direction of C2IFP2 and the level of C1IFP1 Encoder mode C SMSEL 3 b011 The counter counts on both C1IFP1 and C2IFP2 edges rising and falling edges The counting direction is dependent on the C1IFP1 edge direction and C2IFP2 level and C2IFP2 ed...

Page 259: ... TMRx_CH1 or the XOR ed TMRx_CH1 TMRx_CH2 and TMRx_CH3 The sources of C2IRAW C3IRAW and C4IRAW are TMRx_CH2 TMRx_CH3 and TMRx_CH4 respectively CxIRAW inputs digital filter and outputs filtered CxIF signal The digital filter uses the CxDF bit to program sampling frequency and sampling times CxIF inputs edge detector and outputs the CxIFPx signal after edge selection The edge selection depends on bo...

Page 260: ...orded value with the current counter value and the CxRF is set to 1 To capture the rising edge of C1IN input following the configuration procedure mentioned below Set C1C 01 in the TMRx_CxDT register to select the C1IN as channel 1 input Set the filter bandwidth of C1IN signal CxDF 3 0 Set the active edge on the C1IN channel by writing C1P 0 rising edge in the TMRx_CCTR register Program the captur...

Page 261: ...C1DT register and channel 1 input signal rising edge resets the counter The falling edge of channel 1 input signal triggers capture and saves captured values to the C2DT register The period and duty of channel 1 input signal can be calculated through C1DT and C2DT respectively Figure 14 184 Example of PWM input mode configuration C1P 0 C1CP 0 edge detector C1IF C1IN C1IFP1 pos C2IFP1 STCI C1C 2 b0...

Page 262: ...K register to enable TMRx output Set the corresponding GPIO of TMR output channel as the multiplexed mode Set the TMREN bit in the TMRx_CTRL1 register to enable TMRx counter PWM mode B Set CxOCTRL 3 b111 to enable PWM mode B In upcounting when TMRx_C1DT TMRx_CVAL C1ORAW outputs low otherwise outputs high In downcounting when TMRx_C1DT TMRx_CVAL C1ORAW outputs high otherwise outputs low Forced outp...

Page 263: ...counter only counts only one cycle and the output signal sends only one pulse Figure 14 217 C1ORAW toggles when counter value matches the C1DT value 0 1 2 3 31 32 0 1 2 3 31 32 0 1 2 3 COUNTER 31 32 0 1 PR 15 0 C1ORAW TMR_CLK 0 DIV 15 0 32 011 C1OCTRL 2 0 3 C1DT 15 0 Figure 14 228 Upcounting mode and PWM mode A 0 1 2 3 31 32 0 1 2 3 31 32 0 1 2 3 COUNTER 31 32 0 1 PR 15 0 C1ORAW TMR_CLK 0 DIV 15 0...

Page 264: ...S 3 b111 TRGOUT outputs C4ORAW signal CxORAW clear When the CxOSEN bit is set to 1 the CxORAW signal for a given channel is cleared by applying a high level to the EXT input The CxORAW signal remains unchanged until the next overflow event This function can only be used in output capture or PWM modes and does not work in forced mode Figure 31 shows the example of clearing CxORAW signal When the EX...

Page 265: ...is mode the counter is controlled by a selected trigger input The counter starts counting when the trigger input is high and stops as soon as the trigger input is low Figure 14 253 Example of suspend mode 0 1 2 3 4 5 6 7 8 9 COUNTER A B C D 10 PR 15 0 TMR_CLK 0 DIV 15 0 32 101 STIS 2 0 101 SMSEL 2 0 CI1F1 TMR_EN CNT_CLK Slave mode Trigger mode The counter can start counting on the rising edge of a...

Page 266: ...ounting period TMRx_PR registers Configure the slave timer trigger input signal TRGIN as master timer output STIS 2 0 in the TMRx_STCTRL register Configure the slave timer to use external clock mode A SMSEL 2 0 3 b111 in the TMRx_STCTRL register Set TMREN 1 in both master timer and slave timer to enable them Using master timer to start slave timer Configure master timer output signal TRGOUT as an ...

Page 267: ...rigger mode SMSEL 3 b110 in the TMR2_STCTRL register Figure 14 297 Starting master and slave timers synchronously by an external trigger COUNTER PR 15 0 TMREN TMR_CLK 0 DIV 15 0 32 22 PR 15 0 TRGIN 1 21 22 0 1 2 3 21 COUNTER 0 1 2 3 22 0 0 DIV 15 0 TMR_CLK Master TMR Slave TMR 1 31 32 0 1 2 3 31 0 1 2 3 32 0 TMR_EN 14 2 3 6Debug mode When the microcontroller enters debug mode CortexTM M4F core hal...

Page 268: ...bled Bit 6 5 TWCMSEL 0x0 rw Two way counting mode selection 00 One way counting mode depending on the OWCDIR bit 01 Two way counting mode1 count up and down alternately the output flag bit is set only when the counter counts down 10 Two way counting mode2 count up and down alternately the output flag bit is set only when the counter counts up 11 Two way counting mode3 count up and down alternately...

Page 269: ...escription Bit 15 ESP 0x0 rw External signal polarity 0 High or rising edge 1 Low or falling edge Bit 14 ECMBEN 0x0 rw External clock mode B enable This bit is used to enable external clock mode B 0 Disabled 1 Enabled Bit 13 12 ESDIV 0x0 rw External signal divide This field is used to select the frequency division of an external trigger 00 Normal 01 Divided by 2 10 Divided by 4 11 Divided by 8 Bit...

Page 270: ...t is generated at the rising edge of the TRGIN input 111 External clock mode A Rising edge of the TRGIN input clocks the counter Note Please refer to count mode section for the details on encoder mode A B C 14 2 4 4 TMR2 to TMR5 DMA interrupt enable register TMRx_IDEN Bit Register Reset value Type Description Bit 15 Reserved 0x0 resd Kept at its default value Bit 14 TDEN 0x0 rw Trigger DMA request...

Page 271: ... by writing 0 0 No trigger event occurs 1 Trigger event is generated Trigger event an active edge is detected on TRGIN input or any edge in suspend mode Bit 5 Reserved 0x0 resd Kept at its default value Bit 4 C4IF 0x0 rw0c Channel 4 interrupt flag Please refer to C1IF description Bit 3 C3IF 0x0 rw0c Channel 3 interrupt flag Please refer to C1IF description Bit 2 C2IF 0x0 rw0c Channel 2 interrupt f...

Page 272: ...1 Output compare mode Bit Register Reset value Type Description Bit 15 C2OSEN 0x0 rw Channel 2 output switch enable Bit 14 12 C2OCTRL 0x0 rw Channel 2 output control Bit 11 C2OBEN 0x0 rw Channel 2 output buffer enable Bit 10 C2OIEN 0x0 rw Channel 2 output enable immediately Bit 9 8 C2C 0x0 rw Channel 2 configuration This field is used to define the direction of the channel 2 input or output and th...

Page 273: ...nput or output and the selection of input pin when C1EN 0 00 Output 01 Input C1IN is mapped on C1IFP1 10 Input C1IN is mapped on C2IFP1 11 Input C1IN is mapped on STCI This mode works only when the internal trigger input is selected by STIS Input capture mode Bit Register Reset value Type Description Bit 15 12 C2DF 0x0 rw Channel 2 digital filter Bit 11 10 C2IDIV 0x0 rw Channel 2 input divider Bit...

Page 274: ...field is used to define the direction of the channel 1 input or output and the selection of input pin when C4EN 0 00 Output 01 Input C4IN is mapped on C4IFP4 10 Input C4IN is mapped on C3IFP4 11 Input C4IN is mapped on STCI This mode works only when the internal trigger input is selected by STIS Bit 7 C3OSEN 0x0 rw Channel 3 output switch enable Bit 6 4 C3OCTRL 0x0 rw Channel 3 output control Bit ...

Page 275: ...0 rw Channel 2 polarity Please refer to C1P description Bit 4 C2EN 0x0 rw Channel 2 enable Please refer to C1EN description Bit 3 2 Reserved 0x0 resd Kept at its default value Bit 1 C1P 0x0 rw Channel 1 polarity When the channel 1 is configured as output mode 0 C1OUT is active high 1 C1OUT is active low When the channel 1 is configured as input mode 0 C1IN active edge is on its rising edge When us...

Page 276: ...mpared with the CVAL value Whether the written value takes effective immediately depends on the C1OBEN bit and the corresponding output is generated on C1OUT as configured 14 2 4 14 TMR2 to TMR5 channel 2 data register TMRx_C2DT Bit Register Reset value Type Description Bit 31 16 C2DT 0x0000 rw Channel 2 data register When TMR2 or TMR5 enables plus mode the PMEN bit in the TMR_CTRL1 register the C...

Page 277: ...er bytes This field defines the number of DMA transfers 00000 1 byte 00001 2 bytes 00010 3 bytes 00011 4 bytes 10000 17 bytes 10001 18 bytes Bit 7 5 Reserved 0x0 resd Kept at its default value Bit 4 0 ADDR 0x00 rw DMA transfer address offset ADDR is defined as an offset starting from the address of the TMRx_CTRL1 register 00000 TMRx_CTRL1 00001 TMRx_CTRL2 00010 TMRx_STCTRL 14 2 4 18 TMR2 to TMR5 D...

Page 278: ...overflow event trigger event and channel event Figure 14 308 Block diagram of general purpose TMR9 12 TMRx_CH2 TMRx_CH1 Reset mode TMRx_DIV CNT counter CH2 edge detector CH2 filter C2IFP2 C2IFP1 C2IRAW C1IFP2 CH1 edge detector CH1 filter C1IFP1 C1IRAW STCI STCI C2IN DIV C2IN C1IN DIV C1IN C2DT C2C 0 C1DT C1C 0 IN MODE IN MODE C2C 0 C1C 0 OUT MODE OUT MODE C2DT C1DT Compare C2ORAW C1ORAW Output2 co...

Page 279: ...011 CI1FP1 CI2FP2 CK_INT form CRM DIV_counter CK_CNT CNT_counter Internal clock CK_INT By default the CK_INT divided by the prescaler is used to drive the counter to start counting The configuration process is as follows Set the CLKDIV 1 0 bit in the TMRx_CTRL1 register to set the CK_INT frequency Set the TWCMSEL 1 0 bit in the TMRx_CTRL1 register to select count mode If the one way count directio...

Page 280: ...gister Set counting period through the PR 15 0 in TMRx_PR register Enable counter through the TMREN bit in TMRx_CTRL1 register Figure 14 42 Block diagram of external clock mode A C1IFP2 C1IFP1 C1INC ISx CK_DIV Trigger select Slave mode control External clock control CI1RAW Filter Edge detector C2IF_Rising C2IF_Falling Polarity selection Note The delay between the signal on the input side and the a...

Page 281: ...ter and select external clock mode A Set the TMREN bit in the TMRx_CTRL1 register to enable TMRx counter Figure 14 44 Counter timing with prescaler value changing from 1 to 4 TMR_CLK CK_CNT COUNTER OVFIF DIV 15 0 18 17 19 1A 1B 1C 0 3 00 01 Clear PR 15 0 1C Table 14 7 TMRx internal trigger connection Slave controller IS0 STIS 000 IS1 STIS 001 IS2 STIS 010 IS3 STIS 011 TMR9 TMR2_TRGOUT TMR3_TRGOUT ...

Page 282: ...troller in reset mode trigger the generation of an overflow event When the OVFS bit is set only counter overflow underflow triggers an overflow event Setting TMREN 1 to enable the timer to start counting Base on synchronization logic however the actual enable signal TMR_EN is set 1 clock cycle after the TMREN is set Upcounting mode In upcounting mode the counter counts from 0 to the value programm...

Page 283: ... digital filter uses the CxDF bit to program sampling frequency and sampling times CxIF inputs edge detector and outputs the CxIFPx signal after edge selection The edge selection depends on both CxP and CxCP bits It is possible to select input rising edge falling edge or both edges CxIFPx inputs capture signal selector and outputs the CxIN signal after capture signal selection The capture signal s...

Page 284: ...g the configuration procedure mentioned below Set C1C 01 in the TMRx_CxDT register to select the C1IN as channel 1 input Set the filter bandwidth of C1IN signal CxDF 3 0 Set the active edge on the C1IN channel by writing C1P 0 rising edge in the TMRx_CCTR Register Program the capture frequency division of C1IN signal C1DIV 1 0 Enable channel 1 input capture C1EN 1 If needed enable the relevant int...

Page 285: ... C1IF C1IN C1IFP1 pos C2IFP1 STCI C1C 2 b01 C1IRAW filter C1DF C1EN Capture trigger C1INC IS3 IS2 IS1 CI2FP2 STIS 3 b101 Trigger mode Hang mode Reset mode SMSEL 3 b110 C2P 1 C2CP 0 edge detector C2IN C1IFP2 neg C2IFP2 STCI C2EN Capture trigger C2C 2 b10 Capture Capture CNT counter C1DT C2DT reset CH1 period CH1 high level time IS0 Figure 14 51 PWM input mode A 0 1 2 3 4 5 6 7 8 9 A 0 1 2 COUNTER C...

Page 286: ...y Set the CxEN and CxCEN bits in the TMRx_CCTRL register to enable channel output Set the OEN bit in the TMRx_BRK register to enable TMRx output Set the corresponding GPIO of TMR output channel as the multiplexed mode Set the TMREN bit in the TMRx_CTRL1 register to enable TMRx counter PWM mode B Set CxOCTRL 3 b111 to enable PWM mode B In upcounting when TMRx_C1DT TMRx_CVAL C1ORAW outputs low other...

Page 287: ...e pulse PWM mode B The counter only counts only one cycle and the output signal sends only one pulse Figure 14 383 C1ORAW toggles when counter value matches the C1DT value 0 1 2 3 31 32 0 1 2 3 31 32 0 1 2 3 COUNTER 31 32 0 1 PR 15 0 C1ORAW TMR_CLK 0 DIV 15 0 32 011 C1OCTRL 2 0 3 C1DT 15 0 Figure 14 394 Upcounting mode and PWM mode A 0 1 2 3 31 32 0 1 2 3 31 32 0 1 2 3 COUNTER 31 32 0 1 PR 15 0 C1...

Page 288: ...e 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 COUNTER 30 31 32 0 PR 15 0 CI1F1 TMR_CLK 0 DIV 15 0 32 101 STIS 2 0 OVFIF TRGIF 100 SMSEL 2 0 Slave mode Suspend mode In this mode the counter is controlled by a selected trigger input The counter starts counting when the trigger input is high and stops as soon as the trigger input is low Figure 14 427 Example of suspend mode 0 1 2 3 4 5 6 7 8 9 COUNTER A B C ...

Page 289: ...er name Register Reset value TMRx_CTRL1 0x00 0x0000 TMRx_STCTRL 0x08 0x0000 TMRx_IDEN 0x0C 0x0000 TMRx_ISTS 0x10 0x0000 TMRx_SWEVT 0x14 0x0000 TMRx_CM1 0x18 0x0000 TMRx_CCTRL 0x20 0x0000 TMRx_CVAL 0x24 0x0000 TMRx_DIV 0x28 0x0000 TMRx_PR 0x2C 0x0000 TMRx_C1DT 0x34 0x0000 0000 TMRx_C2DT 0x38 0x0000 0000 14 3 4 1 TMR9 and TMR12 control register1 TMRx_CTRL1 Bit Register Reset value Type Description B...

Page 290: ...red input 2 C1IF2 111 Reserved Please refer to Table 14 7 for more information on ISx for each timer Bit 3 Reserved 0x0 resd Kept at its default value Bit 2 0 SMSEL 0x0 rw Subordinate TMR mode selection 000 Slave mode is disabled 001 Encoder mode A 010 Encoder mode B 011 Encoder mode C 100 Reset mode Rising edge of the TRGIN input reinitializes the counter 101 Suspend mode The counter starts count...

Page 291: ...set by hardware on a capture event It is cleared by software or read access to the TMRx_C1DT 0 No capture event occurs 1 Capture event is generated If the channel 1 is configured as output mode This bit is set by hardware on a compare event It is cleared by software 0 No compare event occurs 1 Compare event is generated Bit 0 OVFIF 0x0 rw0c Overflow interrupt flag This bit is set by hardware on an...

Page 292: ...ted by STIS register Bit 7 Reserved 0x0 resd Kept at its default value Bit 6 4 C1OCTRL 0x0 rw Channel 1 output control This field defines the behavior of the original signal C1ORAW 000 Disconnected C1ORAW is disconnected from C1OUT 001 C1ORAW is high when TMRx_CVAL TMRx_C1DT 010 C1ORAW is low when TMRx_CVAL TMRx_C1DT 011 Switch C1ORAW level when TMRx_CVAL TMRx_C1DT 100 C1ORAW is forced low 101 C1O...

Page 293: ...digital filter of the channel 1 N stands for the number of filtering indicating that the input edge can pass the filter only after N sampling events 0000 No filter sampling is done at f𝐷𝑇𝑆 1000 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐷𝑇𝑆 8 N 6 0001 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐶𝐾_𝐼𝑁𝑇 N 2 1001 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐷𝑇𝑆 8 N 8 0010 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐶𝐾_𝐼𝑁𝑇 N 4 1010 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐷𝑇𝑆 16 N 5 0011 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐶𝐾_𝐼𝑁𝑇 N 8 1011 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐷𝑇𝑆 16 N 6 0100 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐷𝑇𝑆 2 N ...

Page 294: ...andard CxOUT channel depends on the CxOUT channel state and the GPIO and IOMUX registers 14 3 4 8 TMR9 and TMR12 counter value TMRx_CVAL Bit Register Reset value Type Description Bit 15 0 CVAL 0x0000 rw Counter value 14 3 4 9 TMR9 and TMR12 division value TMRx_DIV Bit Register Reset value Type Description Bit 15 0 DIV 0x0000 rw Divider value The counter clock frequency fCK_CNT fTMR_CLK DIV 15 0 1 ...

Page 295: ...00 0x0000 TMRx_IDEN 0x0C 0x0000 TMRx_ISTS 0x10 0x0000 TMRx_SWEVT 0x14 0x0000 TMRx_CM1 0x18 0x0000 TMRx_CCTRL 0x20 0x0000 TMRx_CVAL 0x24 0x0000 TMRx_DIV 0x28 0x0000 TMRx_PR 0x2C 0x0000 TMRx_C1DT 0x34 0x0000 14 3 5 1 TMR10 TMR11 TMR13 and TMR14 control register1 TMRx_CTRL1 Bit Register Reset value Type Description Bit 15 10 Reserved 0x00 resd Kept at its default value Bit 9 8 CLKDIV 0x0 rw Clock div...

Page 296: ...1 C1IF 0x0 rw0c Channel 1 interrupt flag If the channel 1 is configured as input mode This bit is set by hardware on a capture event It is cleared by software or read access to the TMRx_C1DT 0 No capture event occurs 1 Capture event is generated If the channel 1 is configured as output mode This bit is set by hardware on a compare event It is cleared by software 0 No compare event occurs 1 Compare...

Page 297: ... 0 C1ORAW is high once TMRx_C1DT TMRx_CVAL else low OWCDIR 1 C1ORAW is low once TMRx_ C1DT TMRx_CVAL else high 111 PWM mode B OWCDIR 0 C1ORAW is low once TMRx_ C1DT TMRx_CVAL else high OWCDIR 1 C1ORAW is high once TMRx_ C1DT TMRx_CVAL else low Note In the configurations other than 000 the C1OUT is connected to C1ORAW The C1OUT output level is not only subject to the changes of C1ORAW but also the ...

Page 298: ...ivider 00 No divider An input capture is generated at each active edge 01 An input compare is generated every 2 active edges 10 An input compare is generated every 4 active edges 11 An input compare is generated every 8 active edges Note the divider is reset once C1EN 0 Bit 1 0 C1C 0x0 rw Channel 1 configuration This field is used to define the direction of the channel 1 input or output and the se...

Page 299: ...ency fCK_CNT fTMR_CLK DIV 15 0 1 DIV contains the value written at an overflow event 14 3 5 9 TMR10 TMR11 TMR13 and TMR14 period register TMRx_PR Bit Register Reset value Type Description Bit 15 0 PR 0x0000 rw Period value This defines the period value of the TMRx counter The timer stops working when the period value is 0 14 3 5 10 TMR10 TMR11 TMR13 and TMR14 channel 1 data register TMRx_C1DT Bit ...

Page 300: ...K Clock failure event From clock control CSS Clock Security System TMRx_BRK TMRx_CH4 TMRx_CH3 TMRx_CH2 TMRx_CH1 TMRX_EXT Polarity selection Polarity selection edge detector prescaler Reset mode Encoder interface TMRx_DIV CNT counter CH4 edge detector C4DT CH4 filter CH3 edge detector CH3 filter C4IFP4 C4IFP3 C4IRAW C3IFP4 C3IFP3 C3IRAW CH2 edge detector CH2 filter C2IFP2 C2IFP1 C2IRAW C1IFP2 CH1 e...

Page 301: ...03 04 05 06 07 overflow OVFIF External clock TRGIN EXT The counter clock can be provided by two external clock sources namely TRGIN and EXT signals SMSEL 3 b111 External clock mode A is selected Select an external clock source TRGIN signal by setting the STIS 2 0 bit to drive the counter to start counting The external clock sources include C1INC STIS 3 b100 channel 1 rising edge and falling edge C...

Page 302: ...requency division through the ESDIV 1 0 bit in TMRx_STCTRL register Set external signal filter through the ESF 3 0 bit in TMRx_STCTRL register Enable external clock mode B through the ECMBEN bit in TMRx_STCTR register Set counting frequency through the DIV 15 0 bit in TMRx_DIV register Set counting period through the PR 15 0 bit in TMRx_PR register Enable counter through the TMREN in TMRx_CTRL1 re...

Page 303: ...h timer consists of a 16 bit prescaler which is used to generate the CK_CNT that enables the counter to count The frequency division relationship between the CK_CNT and TMR_CLK can be adjusted by setting the value of the TMRx_DIV register The prescaler value can be modified at any time but it takes effect only when the next overflow event occurs The internal trigger input is configured as follows ...

Page 304: ...rflow event is generated by default Set OVFEN 1 in the TMRx_CTRL1 to disable generation of update events The OVFS bit in the TMRx_CTRL1 register is used to select overflow event source By default counter overflow underflow setting OVFSWTR bit and the reset signal generated by the slave timer controller in reset mode trigger the generation of an overflow event When the OVFS bit is set only counter ...

Page 305: ...5 0 Clear Up down counting mode Set CMSEL 1 0 2 b00 in the TMRx_CTRL1 register to enable up down counting mode In this mode the counter counts up down alternatively When the counter counts from the value programmed in the TMRx_PR register down to 1 an underflow event is generated and then restarts counting from 0 when the counter counts from 0 to the value of the TMRx_PR register 1 an overflow eve...

Page 306: ... generated when the repetition counter reaches 0 The frequency of the overflow event can be adjusted by setting the repetition counter value Figure 14 72 OVFIF in upcounting mode and up down counting mode 0 1 2 3 31 32 0 1 2 3 31 32 0 1 2 3 COUNTER 31 32 0 1 2 RPR 7 0 2 1 0 RPR_CNT overflow OVFIF 2 0 1 2 3 31 32 31 30 2F 1 0 1 2 3 COUNTER 31 32 31 2F 2 RPR 7 0 2 1 0 RPR_CNT overflow OVFIF 2 30 1 0...

Page 307: ...tion is dependent on the C1IFP1 edge direction and C2IFP2 level and C2IFP2 edge direction and C1IFP1 level To use encoder mode follow the procedures below Set channel 1 input signal filtering through the C1DF 3 0 bit in the TMRx_CM1 register Set channel 1 input signal active level through the C1P bit in the TMRx_CCTRL register Set channel 2 input signal filtering through the C2DF 3 0 bit in the TM...

Page 308: ...ctor and outputs the CxIN signal after capture signal selection The capture signal selection is defined by CxC bit It is possible to select CxIFPx CyIFPx or STCI as CxIN source Of those CyIFPx x y is the CyIFPy signal that is from Y channel and processed by channel x edge detector for example C1IFP2 is the channel 1 s C1IFP1 signal that passed through channel 2 edge detection The STCI comes from s...

Page 309: ...or the C1DEN bit in the TMRx_IDEN register Timer Input XOR function The timer input pins TMRx_CH1 TMRx_CH2 and TMRx_CH3 are connected to the channel 1 selected by setting the C1INSE in the TMRx_CTRL2 register through an XOR gate The XOR gate can be used to connect Hall sensors For example connect the three XOR inputs to the three Hall sensors respectively so as to calculate the position and speed ...

Page 310: ...2 STCI C2EN Capture trigger C2C 2 b10 Capture Capture CNT counter C1DT C2DT reset CH1 period CH1 high level time IS0 Figure 14 528 PWM input mode A 0 1 2 3 4 5 6 7 8 9 A 0 1 2 COUNTER C1C CH1 0x1 reset counter and C1DT capture C1P 0x0 C2C 0x2 C2P 0x1 STIS 0x5 SMSEL 0x6 0xA 0x4 C1DT C2DT 0x0 C2DT capture 3 4 5 6 7 8 9 A 0 1 2 14 4 3 4 TMR output function The TMR output consists of a comparator and ...

Page 311: ...TMRx_CVAL C1ORAW outputs low otherwise outputs high To set PWM mode A the following process is recommended Set the TMRx_PR register to set PWM period Set the TMRx_CxDT register to set PWM duty cycle Set CxOCTRL 3 b110 in the TMRx_CM1 CM2 register to set output mode as PWM mode A Set the TMRx_DIV register and set the counting frequency Set the TWCMSEL 1 0 bit in the TMRx_CTRL1 register to set the c...

Page 312: ...n example of output compare mode toggle with C1DT 0x3 When the counter value is equal to 0x3 C1OUT toggles Figure 14 82 gives an example of the combination between upcounting mode and PWM mode A The output signal behaves when PR 0x32 but CxDT is configured with a different value Figure 14 83 gives an example of the combination between up down counting mode and PWM mode A The output signal behaves ...

Page 313: ...ster PTOS 3 b001 TRGOUT outputs counter enable signal PTOS 3 b010 TRGOUT outputs counter overflow event PTOS 3 b011 TRGOUT outputs capture and compare event PTOS 3 b100 TRGOUT outputs C1ORAW signal PTOS 3 b101 TRGOUT outputs C2ORAW signal PTOS 3 b110 TRGOUT outputs C3ORAW signal PTOS 3 b111 TRGOUT outputs C4ORAW signal CxORAW clear When the CxOSEN bit is set to 1 the CxORAW signal for a given chan...

Page 314: ...f the reference signal the rising edge of the CxCOU is delayed compared to the falling edge of the reference signal If the delay is greater than the width of the active output and if C1OUT and C1COUT do not generate corresponding pulses the dead time should be less than the width of the active output Figure 14 86 gives an example of dead time insertion when CxP 0 CxCP 0 OEN 1 CxEN 1 and CxCEN 1 Fi...

Page 315: ...soon as one of the CxEN and CxCEN bits becomes high If the brake interrupt or DMA request is enabled the brake statue flag is set and a brake interrupt or DMA request can be generated If AOEN 1 the OEN bit is automatically set again at the next overflow event Note When the brake input is active the OEN cannot be set nor the status flag BRKIF can be cleared Figure 14 6 TMR output control CxOUT to G...

Page 316: ...BRK AOEN 14 4 3 6 TMR synchronization The timers are linked together internally for timer synchronization Master timer is selected by setting the PTOS 2 0 bit Slave timer is selected by setting the SMSEL 2 0 bit Slave modes include Slave mode Reset mode The counter and its prescaler can be reset by a selected trigger signal An overflow event can be generated when OVFS 0 ...

Page 317: ...e 14 90 Example of suspend mode 0 1 2 3 4 5 6 7 8 9 COUNTER A B C D 10 PR 15 0 TMR_CLK 0 DIV 15 0 32 101 STIS 2 0 101 SMSEL 2 0 CI1F1 TMR_EN CNT_CLK Slave mode Trigger mode The counter can start counting on the rising edge of a selected trigger input TMR_EN 1 Figure 14 91 Example of trigger mode 0 1 2 3 4 5 COUNTER PR 15 0 TMR_CLK 0 DIV 15 0 32 101 STIS 2 0 110 SMSEL 2 0 CI1F1 TMR_EN 6 7 9 10 A B ...

Page 318: ...x0000 TMRx_C3DT 0x3C 0x0000 TMRx_C4DT 0x40 0x0000 TMRx_BRK 0x44 0x0000 TMRx_DMACTRL 0x48 0x0000 TMRx_DMADT 0x4C 0x0000 TMRx_CM3 0x70 0x0000 TMRx_C5DT 0x74 0x0000 14 4 4 1 TMR1 TMR8 and TMR20 control register1 TMRx_CTRL1 Bit Register Reset value Type Description Bit 15 10 Reserved 0x00 resd Kept at its default value Bit 9 8 CLKDIV 0x0 rw Clock division 00 Normal 01 Divided by 2 10 Divided by 4 11 R...

Page 319: ...1 TRGOUT2EN 0x0 rw TRGOUT2 enable 0 TRGOUT2 disabled 1 TRGOUT2 enabled Bit 30 15 Reserved 0x0000 resd Kept at its default value Bit 14 C4IOS 0x0 rw Channel 4 idle output state Bit 13 C3CIOS 0x0 rw Channel 3 complementary idle output state Bit 12 C3IOS 0x0 rw Channel 3 idle output state Bit 11 C2CIOS 0x0 rw Channel 2 complementary idle output state Bit 10 C2IOS 0x0 rw Channel 2 idle output state Bi...

Page 320: ...ncy division of an external trigger 00 Normal 01 Divided by 2 10 Divided by 4 11 Divided by 8 Bit 11 8 ESF 0x0 rw External signal filter This field is used to filter an external signal The external signal can be sampled only after it has been generated N times 0000 No filter sampling by f𝐷𝑇𝑆 0001 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐶𝐾_𝐼𝑁𝑇 N 2 0010 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐶𝐾_𝐼𝑁𝑇 N 4 0011 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐶𝐾_𝐼𝑁𝑇 N 8 0100 f𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺 f𝐷𝑇𝑆 2 N 6 ...

Page 321: ...DEN Bit Register Reset value Type Description Bit 15 Reserved 0x0 resd Kept at its default value Bit 14 TDEN 0x0 rw Trigger DMA request enable 0 Disabled 1 Enabled Bit 13 HALLDE 0x0 rw HALL DMA request enable 0 Disabled 1 Enabled Bit 12 C4DEN 0x0 rw Channel 4 DMA request enable 0 Disabled 1 Enabled Bit 11 C3DEN 0x0 rw Channel 3 DMA request enable 0 Disabled 1 Enabled Bit 10 C2DEN 0x0 rw Channel 2 ...

Page 322: ... cleared by writing 0 0 Inactive level 1 Active level Bit 6 TRGIF 0x0 rw0c Trigger interrupt flag This bit is set by hardware on a trigger event It is cleared by writing 0 0 No trigger event occurs 1 Trigger event is generated Trigger event an active edge is detected on TRGIN input or any edge in suspend mode Bit 5 HALLIF 0x0 rw0c HALL interrupt flag This bit is set by hardware on HALL event It is...

Page 323: ...by software Please refer to C1M description Bit 2 C2SWTR 0x0 wo Channel 2 event triggered by software Please refer to C1M description Bit 1 C1SWTR 0x0 wo Channel 1 event triggered by software This bit is set by software to generate a channel 1 event 0 No effect 1 Generate a channel 1 event Bit 0 OVFSWTR 0x0 wo Overflow event triggered by software This bit is set by software to generate an overflow...

Page 324: ...vel is not only subject to the changes of C1ORAW but also the output polarity set by CCTRL Bit 3 C1OBEN 0x0 rw Channel 1 output buffer enable 0 Buffer function of TMRx_C1DT is disabled The new value written to the TMRx_C1DT takes effect immediately 1 Buffer function of TMRx_C1DT is enabled The value to be written to the TMRx_C1DT is stored in the buffer register and can be sent to the TMRx_C1DT re...

Page 325: ...ed every 4 active edges 11 An input compare is generated every 8 active edges Note the divider is reset once C1EN 0 Bit 1 0 C1C 0x0 rw Channel 1 configuration This field is used to define the direction of the channel 1 input or output and the selection of input pin when C1EN 0 00 Output 01 Input C1IN is mapped on C1IRAW 10 Input C1IN is mapped on C2IRAW 11 Input C1IN is mapped on STCI This mode wo...

Page 326: ...ut C4IN is mapped on C4IFP4 10 Input C4IN is mapped on C3IFP4 11 Input C4IN is mapped on STCI This mode works only when the internal trigger input is selected by STIS Bit 7 4 C3DF 0x0 rw Channel 3 digital filter Bit 3 2 C3IDIV 0x0 rw Channel 3 input divider Bit 1 0 C3C 0x0 rw Channel 3 configuration This field is used to define the direction of the channel 1 input or output and the selection of in...

Page 327: ...14 15 Complementary output channel CxOUT and CxCOUT control bits with brake function Control bit Output state 1 OEN bit FCSODIS bit FCSOEN bit CxEN bit CxCEN bit CxOUT output state CxCOUT output state 1 X 0 0 0 Output disabled no driven by the timer CxOUT 0 Cx_EN 0 Output disabled no driven by the timer CxCOUT 0 CxCEN 0 0 0 1 Output disabled no driven by the timer CxOUT 0 Cx_EN 0 CxORAW polarity C...

Page 328: ...e 14 4 4 11 TMR1 TMR8 and TMR20 division value TMRx_DIV Bit Register Reset value Type Description Bit 15 0 DIV 0x0000 rw Divider value The counter clock frequency fCK_CNT fTMR_CLK DIV 15 0 1 The value of this register is transferred to the actual prescaler register when an overflow event occurs 14 4 4 12 TMR1 TMR8 and TMR20 period register TMRx_PR Bit Register Reset value Type Description Bit 15 0...

Page 329: ...ng output is generated on C3OUT as configured 14 4 4 17 TMR1 TMR8 and TMR20 channel 4 data register TMRx_C4DT Bit Register Reset value Type Description Bit 15 0 C3DT 0x0000 rw Channel 4 data register When the channel 4 is configured as input mode The C4DT is the CVAL value stored by the last channel 4 input event C1IN When the channel 3 is configured as output mode C4DT is the value to be compared...

Page 330: ...ion level 1 The following bits and all bits in level 2 are write protected TMRx_CMx C2OCTRL and C2OBEN Note Once WPC 0 its content remains frozen until the next system reset Bit 7 0 DTC 0x00 rw Dead time configuration This field defines the duration of the dead time insertion The 3 bit MSB of DTC 7 0 is used for function selection 0xx DT DTC 7 0 TDTS 10x DT 64 DTC 5 0 TDTS 2 110 DT 32 DTC 4 0 TDTS...

Page 331: ...pe Description Bit 15 6 Reserved 0x000 resd Kept at its default value Bit 7 C5OSEN 0x0 rw Channel 5 output switch enable Bit 6 4 C5OCTRL 0x0 rw Channel 5 output control Bit 3 C5OBEN 0x0 rw Channel 5 output buffer enable Bit 2 C5OIEN 0x0 rw Channel 5 output immediately enable Bit 1 0 Reserved 0x0 resd Kept at its default value 14 4 4 22 TMR1 TMR8 and TMR20 channel 5 data register TMRx_C5DT Bit Regi...

Page 332: ...ister Figure 15 1 Window watchdog block diagram EN 7 bit window value WIN 6 0 Prescaler 1 2 4 8 7 bit counter CNT 6 0 PCLK 4096 CNT 0x40 reset reload at CNT WIN reset To prevent system reset the counter must be reloaded only when its value is less than the value stored in the window register and greater than 0x40 The WWDT counter is clocked by a divided APB1_CLK with the division factor being defi...

Page 333: ... registers must be accessed by word 32 bits Table 15 2 WWDT register map and reset value Register name Offset Reset value WWDT_CTRL 0x00 0x7F WWDT_CFG 0x04 0x7F WWDT_STS 0x08 0x00 15 5 1 Control register WWDT_CTRL Bit Register Reset value Type Description Bit 31 8 Reserved 0x000000 resd Kept at its default value Bit 7 WWDTEN 0x0 rw1s Window watchdog enable 0 Disabled 1 Enabled This bit is set by s...

Page 334: ...he window register value a reset is generated The counter must be reloaded between 0x40 and WIN 6 0 15 5 3 Status register WWDT_STS Bit Register Reset value Type Description Bit 31 1 Reserved 0x0000 0000 resd Kept at its default value Bit 0 RLDF 0x0 rw0c Reload counter interrupt flag This flag is set when the downcounter reaches 0x40 This bit is set by hardware and cleared by software ...

Page 335: ...lue to avoid the WDT reset WDT write protected The WDT_DIV and WDT_RLD registers are write protected Writing the value 0x5555 to the WDT_CMD register will unlock write protection The update status of these two registers are indicated by the DIVF and RLDF bits in the WDT_STS register If a different value is written to the WDT_CMD register these two registers will be re protected Writing the value 0...

Page 336: ...V 2 0 bits Min timeout ms RLD 11 0 0x000 Max timeout ms RLD 11 0 0xFFF 4 0 0 1 409 6 8 1 0 2 819 2 16 2 0 4 1638 4 32 3 0 8 3276 8 64 4 1 6 6553 6 128 5 3 2 13107 2 256 6 or 7 6 4 26214 4 16 4Debug mode When the microcontroller enters debug mode CortexTM M4F core halted the WDT counter stops counting by setting the WDT_PAUSE in the DEBUG module Refer to Chapter 30 2 for more information 16 5WDT re...

Page 337: ...Standby mode Bit Register Reset value Type Description Bit 31 12 Reserved 0x00000 resd Kept at its default value Bit 11 0 RLD 0xFFF rw Reload value The write protection must be unlocked in order to enable write access to the register The register can be read only when RLDF 0 16 5 4 Status register WDT_STS Reset in Standby mode Bit Register Reset value Type Description Bit 31 2 Reserved 0x0000 0000...

Page 338: ...r two programmable alarms Periodic auto wakeup Reference clock detection Two programmable tamper detection supporting time stamp feature Supports fine calibration and coarse calibration 20 x battery powered registers 5 x interrupts alarm A alarm B periodic auto wakeup tamper detection and time stamp Multiplexed function output calibration clock output alarm event or wakeup event Multiplexe functio...

Page 339: ... necessary to configure a HEXT divider value before switching a clock source to the HEXT 17 3 2 ERTC initialization ERTC register write protection After a power on reset all ERTC registers are write protected Such protection mechanism is not affected by the system reset Write access to the ERTC registers except the ERTC_STS 14 8 ERTC_TAMP and ERTC_BPRx registers can be enabled by unlocking it To u...

Page 340: ...nt clock will increase by one second If both DECSBS 14 0 and ADDIS bit are configured the clock will increase by a fraction of a second Time latency ADD1S 0 DECSBS DIVB 1 Time advance ADD1S 1 1 DECSBS DIVB 1 Note To avoid subsecond overflow SBS 15 0 must be asserted before setting the ERTC_TADJ register Reference clock detection and coarse digital calibration cannot be used at the same time Thus w...

Page 341: ... alarm clock A or alarm clock B by setting ALAEN 0 or ALBEN 0 2 Wait until the ALAWF or ALBWF bit is set to enable write access to the alarm clock A or B 3 Configure alarm clock A or B registers ERTC_ALA ERTC_ALASBS and ERTC_ALB ERTC_ALBSBS 4 Enable alarm clock A or B by setting ALAEN 1 or ALBEN 1 Note If MASK1 0 in the ERTC_ALA or ERTC_ALB the alarm clock can work normally only when the DIVB valu...

Page 342: ...asked during the 220 ERTC_CLK cycles A maximum of 511 pulses can be removed When the ADD is set 512 pulses can be inserted during the 220 ERTC_CLK cycles When DEC 8 0 and ADD are sued together a deviation ranging from 511 to 512 ERTC_CLK cycles can be added during the 220 ERTC_CLK cycles The effective calibrated frequency FSCAL FSCAL FERTC_CLK 1 512 x ADD DEC 2 DEC 512 x ADD 20 When the divider A ...

Page 343: ...rupt can be generated when a time stamp event occurs Usage of time stamp 1 How to enable time stamp when a valid edge is detected on a tamper pin Select a time stamp in by setting the TSPIN bit Select a rising edge or falling edge to trigger time stamp by setting the TSEDG bit Enable time stamp by setting TSEN 1 2 How to save time stamp on a tamper event Configure tamper detection registers Enable...

Page 344: ...etection pin turns to low level before tamper detection is enabled then a tamper event will be detected right after the tamper detection is enabled Note Tamper detection is still active even when the VDD power is OFF 17 3 8 Multiplexed function output ERTC provides a set of multiplexed function output for the following events 1 Clocks calibrated OUTSEL 0 and CALOEN 1 Output 512Hz CALOSEL 0 Output ...

Page 345: ...lock A ALAF ALAIEN 17 Alarm clock B ALBF ALBIEN 17 Periodic automatic wakeup WATF WATIEN 22 Time stamp TSF TSIEN 21 Tamper event TP1F TP2F TPIEN 21 17 4ERTC registers These peripheral registers must be accessed by words 32 bits ERTC registers are 16 bit addressable registers Table 17 4 ERTC register map and reset values Register name Offset Reset value ERTC_TIME 0x00 0x0000 0000 ERTC_DATE 0x04 0x0...

Page 346: ...x0 resd Kept at its default value Bit 6 4 ST 0x0 rw Second tens Bit 3 0 SU 0x0 rw Second units 17 4 2 ERTC date register ERTC_DATE Bit Register Reset value Type Description Bit 31 24 Reserved 0x00 resd Kept at its default value Bit 23 20 YT 0x0 rw Year tens Bit 19 16 YU 0x0 rw Year units Bit 15 13 WK 0x1 rw Week day 0 Forbidden 1 Monday 2 Tuesday 3 Wednesday 4 Thursday 5 Friday 6 Saturday 7 Sunday...

Page 347: ...terrupt enable 0 Wakeup timer interrupt disable 1 Wakeup timer interrupt enabled Bit 13 ALBIEN 0x0 rw Alarm B interrupt enable 0 Alarm B interrupt disabled 1 Alarm B interrupt enabled Bit 12 ALAIEN 0x0 rw Alarm A interrupt enable 0 Alarm A interrupt disabled 1 Alarm A interrupt enabled Bit 11 TSEN 0x0 rw Timestamp enable 0 Timestamp disabled 1 Timestamp enabled Bit 10 WATEN 0x0 rw Wakeup timer ena...

Page 348: ...0c Tamper detection 2 flag 0 No tamper event 1 Tamper event occurs Bit 13 TP1F 0x0 rw0c Tamper detection 1 flag 0 No tamper event 1 Tamper event occurs Bit 12 TSOF 0x0 rw0c Timestamp overflow flag 0 No timestamp overflow 1 Timestamp overflow occurs If a new time stamp event is detected when time stamp flag TSF is already set this bit will be set by hardware Bit 11 TSF 0x0 rw0c Timestamp flag 0 No ...

Page 349: ...atically cleared at the end of time adjustment Bit 2 WATWF 0x1 ro Wakeup timer register allows write flag 0 Wakeup timer register configuration not allowed 1 Wakeup timer register configuration allowed Bit 1 ALBWF 0x1 ro Alarm B register allows write flag 0 Alarm B register write operation not allowed 1 Alarm B register write operation allowed Bit 0 ALAWF 0x1 ro Alarm A register allows write flag ...

Page 350: ... 21 20 HT 0x0 rw Hour tens Bit 19 16 HU 0x0 rw Hour units Bit 15 MASK2 0x0 rw Minute mask 0 No minute mask 1 Alarm clock doesn t care about minutes Bit 14 12 MT 0x0 rw Minute tens Bit 11 8 MU 0x0 rw Minute units Bit 7 MASK1 0x0 rw Second mask 0 No second mask 1 Alarm clock doesn t care about seconds Bit 6 4 ST 0x0 rw Second tens Bit 3 0 SU 0x0 rw Second units 17 4 9 ERTC alarm clock B register ERT...

Page 351: ...cy ERTC_CLK DIVA 1 17 4 12ERTC time adjustment register ERTC_TADJ Bit Register Reset value Type Description Bit 31 ADD1S 0x0 wo Add 1 second 0 No effect 1 Add one second This bit can be written only when TADJF 0 It is intended to be used with DECSBS in order to fine tune the time Bit 30 15 Reserved 0x0000 resd Kept at its default value Bit 14 0 DECSBS 0x0000 wo DECSBS 14 0 Decrease sub second valu...

Page 352: ... Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit 15 ADD 0x0 rw Add ERTC clock 0 No ERTC clock added 1 One ERTC_CLK is inserted every 211 ERTC_CLK cycles Bit 14 CAL8 0x0 rw 8 second calibration period 0 No effect 1 8 second calibration Bit 13 CAL16 0x0 rw 16 second calibration period 0 No effect 1 16 second calibration Bit 12 9 Reserved 0x0 resd Kept at its...

Page 353: ...C_CLK 512 7 ERTC_CLK 256 Bit 7 TPTSEN 0x0 rw Tamper detection timestamp enable 0 Tamper detection timestamp disabled 1 Tamper detection timestamp enabled Save timestamp on a tamper event Bit 6 5 Reserved 0x0 resd Kept at its default value Bit 4 TP2EDG 0x0 rw Tamper detection 2 valid edge If TPFLT 0 0 Rising edge 1 Falling edge If TPFLT 0 0 Low 1 High Bit 3 TP2EN 0x0 rw Tamper detection 2 enable 0 ...

Page 354: ...B subsecond register ERTC_ALBSBS Bit Register Reset value Type Description Bit 31 28 Reserved 0x0 resd Kept at its default value Bit 27 24 SBSMSK 0x0 rw Sub second mask 0 No comparison Alarm B doesn t care about subseconds 1 SBS 0 is compared 2 SBS 1 0 are compared 3 SBS 2 0 are compared 14 SBS 13 0 are compared 15 SBS 14 0 are compared Bit 23 15 Reserved 0x000 rw Kept at its default value Bit 14 ...

Page 355: ...r more information ADC input range VREF VIN VREF In terms of digital control Regular channels and preempted channels with different priority Regular channels and preempted channels both have their own trigger detection circuit Each channel can independently define its own sampling time Conversion sequence supports various conversion modes Oversampling Optional data alignment mode Programmable volt...

Page 356: ...Temp sensor ADCx_IN1 ADCx_IN0 ADCx_IN15 INTRV VBAT ADC prescaler ADCDIV Analog to digital converter Preempted data register 4 16 bits Channel manegement Preempted channels Ordinary channels Address Data bus Data management Oversampler GPIO OCCE flag PCCE flag ADC interrupt to NVIC OCCOIEN DMA request VSSA VDDA V REF VREF Ordinary data register 16 bits Trigger detection VMOR flag OCCO flag OCCEIEN ...

Page 357: ... 1 1 Internal temperature sensor The temperature sensor is connected to ADC1_IN16 Before the temperature sensor channel conversion it is required to enable the ITSRVEN bit in the ADC_CTRL2 register and wait after power on time Obtain the temperature using the following formula Temperature in C V 25 VSENSE Avg_Slope 25 Where V25 VSENSE value for 25 C and Avg_Slope Average Slope for curve between Te...

Page 358: ...2 register to supply the ADC and wait until the RDF flab is set before starting ADC conversion Clear the ADCEN bit will stop the ADC conversion and result in a reset In the meantime the ADC is switched off to save power Calibration After power on the calibration is enabled by setting the ADCAL bit in the ADC_CTRL2 register When the calibration is complete the ADCAL bit is cleared by hardware and t...

Page 359: ...TRG and PCSWTRG bits in the ADC_CTRL2 register or by an external event The external events include timer and pin triggers The OCTESEL and PCTESEL bits in the ADC_CTRL2 register are used to select specific trigger sources as shown in Table 18 1 and Table 18 2 Table 18 1 Trigger sources for ordinary channels OCTESEL Trigger source OCTESEL Trigger source 00000 TMR1_CH1 event 10000 TMR20_TRGOUT event ...

Page 360: ...tion has shorter conversion time A single one conversion time is calculated with the following formula A single one conversion time ADCCLK period sampling time resolution bits 0 5 Example If the CSPTx selects 2 5 period and CRSEL select 12 bit resolution then one conversion needs 2 5 12 5 15 ADCCLK periods If the CSPTx selects 6 5 period and CRSEL select 10 bit resolution then one conversion needs...

Page 361: ...y at the end of the conversion of the ordinary group Figure 18 5 shows an example of the behavior when the automatic preempted group conversion mode works with the ordinary group Figure 18 5 Preempted group auto conversion mode ADC_IN5 ADC_IN0 ADC_IN5 OCLEN 2 OSN1 ADC_IN5 OSN2 ADC_IN0 OSN3 ADC_IN5 Ordinary channel trigger OCCE flag set PCLEN 1 PSN3 ADC_IN14 PSN4 ADC_IN1 ADC_IN14 ADC_IN1 PCCE flag ...

Page 362: ...one trigger event will enable the conversion of all the channels in the sub group Each trigger event selects different sub group in order The partition mode cannot be used with the repetition mode at the same time Figure 18 7 shows an example of the behavior in partition mode for ordinary group and preempted group Figure 18 7 Partition mode ADC_IN5 ADC_IN0 OCLEN 4 OCPCNT 1 OSN1 ADC_IN5 OSN2 ADC_IN...

Page 363: ...d by four times in a single oversampling conversion and the converted data derived from 4 conversions is put together If 6 bit resolution is selected through the OSSSE bit then the cumulative data is divided by 26 and rounded up Table 18 3 Correlation between maximum cumulative data oversampling multiple and shift digits Oversampling multiple 2x 4x 8x 16x 32x 64x 128x 256x Max cumulative data 0x1F...

Page 364: ...rigger 1st 2nd 3rd ADC_IN0 ADC_IN4 ADC_IN5 ADC_IN0 ADC_IN0 3rd 4th Ordinary Preempted ADC_IN0 ADC_IN0 Preempted trigger Oversampling halt Oversampling continue OCCE flag set PCCE flag set Restart mode OOSEN 1 POSEN 0 OOSRSEL 1 OOSTREN 0 Ordinary trigger 1st 2nd 3rd ADC_IN0 ADC_IN4 ADC_IN5 Ordinary Preempted ADC_IN0 ADC_IN0 1st 2nd 3rd ADC_IN0 4th ADC_IN0 OCLEN 0 OSN1 ADC_IN0 PCLEN 1 PSN3 ADC_IN4 P...

Page 365: ...nd ordinary oversampling trigger mode are used simultaneously in 4x oversampling rate and auto conversion of preempted group Figure 18 11 Oversampling of preempted group of channels ADC_IN0 ADC_IN0 PCCE flag set OOSEN 1 POSEN 1 OOSRSEL 0 OOSTREN 0 PCAUTOEN 1 SQEN 1 Ordinary trigger 1st 2nd 3rd ADC_IN0 Ordinary Preempted OCLEN 0 OSN1 ADC_IN0 PCLEN 1 PSN3 ADC_IN4 PSN4 ADC_IN5 ADC_IN0 4th ADC_IN4 ADC...

Page 366: ...sts each time the ADC_OTD register is updated When the EOCSFEN or OCDMAEN is set the ADC will automatically start overflow detection If an overflow event occurs the OCCO flag will be set the ADC stops conversion and the last valid data is stored in the data register If the DMA is used the DMA request remains set so that the DMA can read the last valid data The OCCO flag is cleared by software and ...

Page 367: ...verted data of master salve ADC In a single master slave mode ADC1 acts as a master while ADC2 as a slave and ADC3 behaves independently In dual master slave mode ADC1 acts as a master while both ADC2 and ADC3 act as slaves Note ADC conversion abort ADABRT cannot be used in master slave mode In this mode each of the ADCEN bit of the ADCs must be cleared in order to stop ADC conversions Note Both t...

Page 368: ..._ODT 7 0 ADC1_ODT 7 0 2nd 16 bit 0 ADC2_ODT 7 0 ADC1_ODT 7 0 Dual slave 1st 16 bit 0 ADC2_ODT 7 0 ADC1_ODT 7 0 2nd 16 bit 0 ADC1_ODT 7 0 ADC3_ODT 7 0 3rd 16 bit 0 ADC3_ODT 7 0 ADC2_ODT 7 0 4th 16 bit 0 ADC2_ODT 7 0 ADC1_ODT 7 0 100 Dual slave 1st 8 bit 0 ADC3_ODT 7 0 ADC2_ODT 7 0 ADC1_ODT 7 0 2nd 8 bit 0 ADC3_ODT 7 0 ADC2_ODT 7 0 ADC1_ODT 7 0 101 Dual slave 1st ADC2_ODT 15 0 ADC1_ODT 15 0 2nd 16 b...

Page 369: ...s mode ADC2 ADC1 Sampling Conversion ADC1 preempted trigger ADC3 ADC1_IN0 ADC1_IN1 ADC1_IN2 ADC2_IN5 ADC2_IN4 ADC2_IN3 ADC3_IN7 ADC3_IN8 ADC3_IN9 ADC1_IN0 ADC1_IN1 ADC1_IN2 ADC2_IN5 ADC2_IN4 ADC2_IN3 ADC3_IN7 ADC3_IN8 ADC3_IN9 PCCE flag set Single slave mode Double slaves mode ADC1 preempted trigger PCCE flag set ADC1 PCLEN 2 PSN2 ADC1_IN0 PSN3 ADC1_IN1 PSN4 ADC1_IN2 ADC2 PCLEN 2 PSN2 ADC2_IN5 PSN...

Page 370: ...s is stopped and one of the ADCs starts the preempted conversion At this point the master will ignore the preempted trigger until the regular conversion is resumed 18 5 4 Regular shift mode MSSEL bit in the ADC_CTRL1 register is used to select regular shift mode on regular group After a master trigger occurs the conversion interval between ADCs is based on the programmed shift length through the M...

Page 371: ...ap and their reset values These peripheral registers must be accessed by word 32 bits Table 18 5 ADC register map and reset values Register name Offset Reset value ADC1_STS 0x000 0x0000 0000 ADC1_CTRL1 0x004 0x0000 0000 ADC1_CTRL2 0x008 0x0000 0000 ADC1_SPT1 0x00C 0x0000 0000 ADC1_SPT2 0x010 0x0000 0000 ADC1_PCDTO1 0x014 0x0000 0000 ADC1_PCDTO2 0x018 0x0000 0000 ADC1_PCDTO3 0x01C 0x0000 0000 ADC1_...

Page 372: ...00 0000 ADC2_PDT2 0x140 0x0000 0000 ADC2_PDT3 0x144 0x0000 0000 ADC2_PDT4 0x148 0x0000 0000 ADC2_ODT 0x14C 0x0000 0000 ADC2_OVSP 0x180 0x0000 0000 ADC2_CALVAL 0x1B4 0x0000 0000 ADC3_STS 0x200 0x0000 0000 ADC3_CTRL1 0x204 0x0000 0000 ADC3_CTRL2 0x208 0x0000 0000 ADC3_SPT1 0x20C 0x0000 0000 ADC3_SPT2 0x210 0x0000 0000 ADC3_PCDTO1 0x214 0x0000 0000 ADC3_PCDTO2 0x218 0x0000 0000 ADC3_PCDTO3 0x21C 0x00...

Page 373: ...dinary channel conversion start flag This bit is set by hardware and cleared by software writing 0 0 No ordinary channel conversion started 1 Ordinary channel conversion has started Bit 3 PCCS 0x0 rw0c Preempted channel conversion start flag This bit is set by hardware and cleared by software writing 0 0 No preempted channel conversion started 1 Preempted channel conversion has started Bit 2 PCCE ...

Page 374: ...2 channels 111 8 channels Note In this mode the preempted group converts only one channel at each trigger Bit 12 PCPEN 0x0 rw Partitioned mode enable on preempted channels 0 Partitioned mode disabled on preempted channels 1 Partitioned mode enabled on preempted channels Bit 11 OCPEN 0x0 rw Partitioned mode enable on ordinary channels This is set and cleared by software to enable or disable partiti...

Page 375: ...Bit 30 26 Reserved 0x00 resd Kept at its default value Bit 30 OCSWTRG 0x0 rw Conversion of ordinary channels triggered by software 0 Conversion of ordinary channels not triggered 1 Conversion of ordinary channels triggered This bit is cleared by software or by hardware as soon as the conversion starts Bit 29 28 OCETE 0x0 rw Ordinary channel external trigger edge select 00 Edge trigger forbidden 01...

Page 376: ...is cleared after the calibration registers are initialized 0 No initialization occurred or initialization completed 1 Enable initialization or initializations is ongoing Bit 2 ADCAL 0x0 rw A D Calibration 0 No calibration occurred or calibration completed 1 Enable calibration or calibration is in process Bit 1 RPEN 0x0 rw Repetition mode enable 0 Repetition mode disabled When SQEN 0 a single conve...

Page 377: ...6 5 cycles 010 12 5 cycles 011 24 5 cycles 100 47 5 cycles 101 92 5 cycles 110 247 5 cycles 111 640 5 cycles 111 239 5 cycles Bit 20 18 CSPT16 0x0 rw Sample time selection of channel ADC_IN16 000 2 5 cycles 001 6 5 cycles 010 12 5 cycles 011 24 5 cycles 100 47 5 cycles 101 92 5 cycles 110 247 5 cycles 111 640 5 cycles Bit 17 15 CSPT15 0x0 rw Sample time selection of channel ADC_IN15 000 2 5 cycles...

Page 378: ...on of channel ADC_IN11 000 2 5 cycles 001 6 5 cycles 010 12 5 cycles 011 24 5 cycles 100 47 5 cycles 101 92 5 cycles 110 247 5 cycles 111 640 5 cycles Bit 2 0 CSPT10 0x0 rw Sample time selection of channel ADC_IN10 000 2 5 cycles 001 6 5 cycles 010 12 5 cycles 011 24 5 cycles 100 47 5 cycles 101 92 5 cycles 110 247 5 cycles 111 640 5 cycles 18 6 5 ADC sampling time register 2 ADC_SPT2 Accessed by ...

Page 379: ...les 110 247 5 cycles 111 640 5 cycles Bit 20 18 CSPT6 0x0 rw Sample time selection of channel ADC_IN6 000 2 5 cycles 001 6 5 cycles 010 12 5 cycles 011 24 5 cycles 100 47 5 cycles 101 92 5 cycles 110 247 5 cycles 111 640 5 cycles Bit 17 15 CSPT5 0x0 rw Sample time selection of channel ADC_IN5 000 2 5 cycles 001 6 5 cycles 010 12 5 cycles 011 24 5 cycles 100 47 5 cycles 101 92 5 cycles 110 247 5 cy...

Page 380: ...01 92 5 cycles 110 247 5 cycles 111 640 5 cycles Bit 2 0 CSPT0 0x0 rw Sample time selection of channel ADC_IN0 000 2 5 cycles 001 6 5 cycles 010 12 5 cycles 011 24 5 cycles 100 47 5 cycles 101 92 5 cycles 110 247 5 cycles 111 640 5 cycles 18 6 6 ADC preempted channel data offset register x ADC_ PCDTOx x 1 4 Accessed by words Bit Register Reset value Type Description Bit 31 12 Reserved 0x00000 resd...

Page 381: ...rdinary sequence register 2 ADC_ OSQ2 Accessed by words Bit Register Reset value Type Description Bit 31 30 Reserved 0x0 resd Kept at its default value Bit 29 25 OSN12 0x00 rw Number of 12th conversion in ordinary sequence Bit 24 20 OSN11 0x00 rw Number of 11th conversion in ordinary sequence Bit 19 15 OSN10 0x00 rw Number of 10th conversion in ordinary sequence Bit 14 10 OSN9 0x00 rw Number of 9t...

Page 382: ...r example if the number is set to 3 it refers to the ADC_IN3 channel If PCLEN is less than 4 the conversion sequence starts from 4 PCLEN For example when ADC_PSQ 21 0 10 00110 00101 00100 00011 it indicates that the scan conversion follows the sequence 4 5 6 not 3 4 5 18 6 13ADC preempted data register x ADC_ PDTx x 1 4 Accessed by words Bit Register Reset value Type Description Bit 31 16 Reserved...

Page 383: ...000 No shift 0001 1 bit 0010 2 bits 0011 3 bits 0100 4 bits 0101 5 bits 0110 6 bits 0111 7 bits 1000 8 bits 1001 1111 Unused Do not configure Bit 4 2 OSRSEL 0x0 rw Oversampling ratio select 000 2x 001 4x 010 8x 011 16x 100 32x 101 64x 110 128x 111 256x Bit 1 POSEN 0x0 rw Preempted oversampling enable 0 Preempted oversampling disabled 1 Preempted oversampling enabled Bit 0 OOSEN 0x0 rw Ordinary ove...

Page 384: ... This bit is the mapping bit of the RDY bit in the ADC2_STS register Bit 13 OCCO2 0x0 ro ADC2 ordinary channel conversion overflow flag This bit is the mapping bit of the OCCO bit in the ADC2_STS register Bit 12 OCCS2 0x0 ro ADC2 ordinary channel conversion start flag This bit is the mapping bit of the OCCS bit in the ADC2_STS register Bit 11 PCCS2 0x0 ro ADC2 preempted channel conversion start fl...

Page 385: ..._CSTS Accessed by words Bit Register Reset value Type Description Bit 31 24 Reserved 0x0000 resd Kept at its default value Bit 23 ITSRVEN 0x0 rw Internal temperature sensor and VINTRV enable 0 Disabled 1 Enabled Bit 22 VBATEN 0x0 rw VBAT enable 0 Disabled 1 Enabled Bit 21 20 Reserved 0x0 resd Kept at its default value Bit 19 16 ADCDIV 0x0 rw ADC division 0000 HCLK 2 0001 HCLK 3 1111 HCLK 17 Note T...

Page 386: ... rw Combined master slave mode select 00000 Non combined mode 00001 Combined ordinary simultaneous preempted simultaneous modes single slave 00010 Combined ordinary simultaneous alternate preempted trigger modes single slave 00011 00100 Unused Do not configure 00101 Preempted simultaneous mode single slave 00110 Ordinary simultaneous mode single slave 00111 Ordinary shift mode single slave 01000 U...

Page 387: ...16 CODTH 0x0000 rw Ordinary conversion high halfword data in master slave mode Note The meanings of data in this field vary from DMA mode to DMA mode Refer to Section 18 5 1 for details Bit 15 0 CODTL 0x0000 rw Ordinary conversion low halfword data in master slave mode Note The meanings of data in this field vary from DMA mode to DMA mode Refer to Section 18 5 1 for details ...

Page 388: ...res A single dual DAC 8 bit or 12 bit digital input Left or right data alignment Noise wave Triangular wave generation Dual DAC or single DAC1 DAC2 independent conversions DMA mode for DAC1 DAC2 Software or external triggers for conversion Input reference voltage VREF 19 3Design tips The following information can be used as DAC design reference Analog module configuration The analog part of the DA...

Page 389: ...y an external event timer counter external interrupt line or by software The DxTRGSEL 2 0 is used to select trigger sources Table 19 1 Trigger source selection Source DxTRGSEL 2 0 Description TMR6_TRGOUT 000 On chip signals TMR8_TRGOUT 001 TMR7_TRGOUT 010 TMR5_TRGOUT 011 TMR2_TRGOUT 100 TMR4_TRGOUT 101 EXINT_9 110 External signals DxSWTRG 111 Software trigger When the DxTRGEN bit is set the data s...

Page 390: ...lar wave counter is incremented at each trigger event Once the maximum amplitude programmed in the DxNBSEL 3 0 is reached the value of this counter is decremented down to 0 then incremented again and so on Meanwhile the value of this counter is then added up to the DHRx register without overflow and the resulting value is loaded into the DAC_DxODT register It is possible to disable reset the trian...

Page 391: ...x0000 0000 DAC_D1ODT 02Ch 0x0000 0000 DAC_D2ODT 030h 0x0000 0000 DAC_STS 034h 0x0000 0000 19 5 1 DAC control register DAC_CTRL Bit Register Reset value Type Description Bit 31 30 Reserved 0x0 resd Kept at its default value Bit 29 D2DMAUDRIEN 0x0 rw DAC2 DMA transfer underrun interrupt enable This bit is set and cleared by software 0 DAC2 DMA transfer underrun interrupt disabled 1 DAC2 DMA transfer...

Page 392: ...after one APB1 clock cycle When the DAC2 trigger is enabled the data written into the DAC_D2DTHx register is transferred into the DAC_ D2ODT register after three APB1 clock cycles If the software trigger is selected it takes one APB1 clock cycle to have the data written into the DAC_D2DTHx register transferred into the DAC_D2ODT register Bit 17 D2OBDIS 0x0 rw DAC2 output buffer disable 0 DAC2 outp...

Page 393: ...nabled Note When the DAC1 trigger is disabled the data written into the DAC_D1DTHx register is transferred into the DAC_D1ODT register after one APB1 clock cycle When the DAC1 trigger is enabled the data written into the DAC_D1DTHx register is transferred into the DAC_ D1ODT register after three APB1 clock cycles If the software trigger is selected it takes one APB1 clock cycle to have the data wr...

Page 394: ...ligned data holding register DAC_ D2DTH12R Bit Register Reset value Type Description Bit 31 12 Reserved 0x00000 resd Kept at its default value Bit 11 0 D2DT12R 0x000 rw DAC2 12 bit right aligned data 19 5 7 DAC2 12 bit left aligned data holding register DAC_ D2DTH12L Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit 15 4 D2DT12L 0x000 rw DAC2 12...

Page 395: ...er DAC_ D1ODT Bit Register Reset value Type Description Bit 31 12 Reserved 0x00000 resd Kept at its default value Bit 11 0 D1ODT 0x000 rw DAC1 output data 19 5 13DAC2 data output register DAC_ D2ODT Bit Register Reset value Type Description Bit 31 12 Reserved 0x00000 resd Kept at its default value Bit 11 0 D2ODT 0x000 rw DAC2 output data 19 5 14DAC status register DAC_STS Bit Register Reset value ...

Page 396: ...fier list mode Supports the identifier mask mode FIFO overrun management Time triggered communication mode 16 bit timers Time stamp on transmission 20 3Baud rate The nominal bit time of the CAN bus consists of three parts as follows Synchronization segment SYNC_SEG This segment has one time unit and its time duration is defined by the BRDIV 11 0 bit in the CAN_BTMG register Bit segment 1 BIT SEGME...

Page 397: ...nt by default and the sampling is performed at the edge location of bit segment 1 and big segment 2 simultaneously During the actual transmission each bit of the CAN nodes has certain phase error due to the oscillator drift transmission delay among the network nodes and noise interference To avoid the impact on the communication the start bit edge and its subsequent falling edge can be synchronize...

Page 398: ... field 2 7 EOF ACK RTR r0 IDE SOF Data frame or remote frame Error frame Inter frame space or overload frame Error flag Error echo Error delimiter 6 6 8 Data frame or remote frame Intermission Suspend transmission Bus idle 3 8 Any frame End of frame or error delimiter or overload delimiter Overload frame Inter frame space or error frame Overload flag Overload echo Overload delimiter 6 6 8 Notes 0 ...

Page 399: ...it interrupt generation TM0TCF 1 TM1TCF 1 TM2TCF 1 TCIEN 1 TX_INT Figure 20 4 Receive interrupt 0 generation RF0MN 00 RFF0MIEN 1 RF0FF 1 RF0FIEN 1 RF0OF 1 RF0OIEN 1 RX0_INT Figure 20 5 Receive interrupt 1 generation RF1MN 00 RFF1MIEN 1 RF1FF 1 RF1FIEN 1 RF1OF 1 RF1OIEN 1 RX1_INT Figure 20 6 Status error interrupt generation EAF 1 EAIEN 1 EPF 1 EPIEN 1 BOF 1 BOIEN 1 SE_INT ETR 6 4 000 and 111 ETRIE...

Page 400: ...FG CAN_FBWCFG and CAN_FRF registers can be modified only when FCS 1 The CAN_FiFBx register can be modified only when FCS 1 or FAENx 0 20 6Functional overview 20 6 1 General description As the number of nodes in the CAN network and the number of messages grows an enhanced filtering mechanism is required to handle all types of messages in order to reduce the processing time of message reception One ...

Page 401: ... is cleared in the CAN_MCTRL register This switch operation is confirmed by hardware clearing the FZC bit in the CAN_MSTS register The CAN controller must be synchronized with the bus Switch to Sleep mode The CAN controller enters Sleep mode if DZEN 1 and FZEN 0 in the CAN_MCTRL register This switch operation is confirmed by hardware setting the DZC bit in the CAN_MSTS register Communication mode ...

Page 402: ...5 CAN_FiFB1 4 3 CAN_FiFB1 2 0 CAN_FiFB2 31 21 CAN_FiFB2 20 19 CAN_FiFB2 18 16 CAN_FiFB2 15 5 AN_FiFB2 4 3 CAN_FiFB2 2 0 SID 10 0 IDT RTR EID 17 15 SID 10 0 IDT RTR EID 17 15 Filtering mode The filter can be configured in identifier mask mode or in identifier list mode by setting the FMSELx bit in the CAN_FMCFG register The mask mode is used to specify which bits must match the pre programmed ident...

Page 403: ... by setting the FCS bit in the CAN_FCTRL register Identifier mask mode or identifier list mode can be selected by setting the FMSELx bit in the CAN_FMCFG register The filter bit width can be configured as two 16 bits or one 32 bits by setting the FBWSELx bit in the CAN_FBWCFG register The filter x is associated with FIFO0 or FIFO1 by setting the FRFSELx bit in the CAN_FRF register The filter banks...

Page 404: ...EF and TMxEF bits in the CAN_TSTS register are used to indicate transmit status and error status TMxTCF bit Transmission complete flag indicating that the data transmission is complete when TMxTCF 1 TMxTSF bit Transmission success flag indicating that the data has been transmitted successfully when TMxTSF 1 TMxALF bit Transmission arbitration lost flag indicating that the data transmission arbitra...

Page 405: ...e Addr a Receive a valid frame b Receive a valid frame c Receive a valid frame d Receive a valid frame e Release a frame f Release a frame Address 2 Address 0 Address 1 Address 2 Address 0 Address 1 Address 2 Address 0 Address 1 Address 2 Address 0 Address 1 Address 2 Address 0 Address 1 Address 2 Read Addr Read Addr Read Addr Read Addr Read Addr Write Addr Write Addr Write Addr Write Addr Write A...

Page 406: ...TMI0 180h 0xXXXX XXXX TMC0 184h 0xXXXX XXXX TMDTL0 188h 0xXXXX XXXX TMDTH0 18Ch 0xXXXX XXXX TMI1 190h 0xXXXX XXXX TMC1 194h 0xXXXX XXXX TMDTL1 198h 0xXXXX XXXX TMDTH1 19Ch 0xXXXX XXXX TMI2 1A0h 0xXXXX XXXX TMC2 1A4h 0xXXXX XXXX TMDTL2 1A8h 0xXXXX XXXX TMDTH2 1ACh 0xXXXX XXXX RFI0 1B0h 0xXXXX XXXX RFC0 1B4h 0xXXXX XXXX RFDTL0 1B8h 0xXXXX XXXX RFDTH0 1BCh 0xXXXX XXXX RFI1 1C0h 0xXXXX XXXX RFC1 1C4h ...

Page 407: ...Time triggered communication mode enable 0 Time triggered communication mode disabled 1 Time triggered communication mode enabled Bit 6 AEBOEN 0x0 rw Automatic exit bus off enable 0 Automatic exit bus off disabled 1 Automatic exit bus off enabled Note When Automatic exit bus off mode is enabled the hardware will automatically leave bus off mode as soon as an exit timing is detected on the CAN bus ...

Page 408: ...rdware 20 7 1 2CAN master status register CAN_MSTS Bit Register Reset value Type Description Bit 31 12 Reserved 0x00000 resd Kept at its default value Bit 11 REALRX 0x1 ro Real time level on RX pin 0 Low 1 High Bit 10 LSAMPRX 0x1 ro Last sample level on RX pin 0 Low 1 High Note This value keeps updating with the REALRX Bit 9 CURS 0x0 ro Current receive status 0 No reception occurs 1 Reception is i...

Page 409: ...reeze mode confirm 0 The CAN is not in Freeze mode 1 The CAN is in Freeze mode Note This bit is used to decide whether the CAN is in Freeze mode or not This bit acknowledges the Freeze mode request generated by software The Freeze mode can be entered only when the current CAN activity transmission or reception is completed For this reason the software acknowledges the entry of Freeze mode after th...

Page 410: ...ailbox 2 is free Bit 22 20 Reserved 0x0 resd Kept at its default value Bit 19 TM2TEF 0x0 rw1c Transmit mailbox 2 transmission error flag 0 No error 1 Mailbox 2 transmission error Note This bit is set when the mailbox 2 transmission error occurred It is cleared by software writing 1 or by hardware at the start of the next transmission Bit 18 TM2ALF 0x0 rw1c Transmit mailbox 2 arbitration lost flag ...

Page 411: ...s in progress 1 Transmission is completed Note This bit is set by hardware when the transmission abort request on mailbox 1 has been completed It is cleared by software writing 1 or by hardware when a new transmission request is received Clearing this bit will clear the TM1TSF TM1ALF and TM1TEF bits of mailbox 1 Bit 7 TM0CT 0x0 rw1s Transmit mailbox 0 cancel transmit 0 No effect 1 Mailbox 0 cancel...

Page 412: ... second message Bit 4 RF0OF 0x0 rw1c Receive FIFO 0 overflow flag 0 No overflow 1 Receive FIFO 0 overflow Note This bit is set by hardware when a new message has been received and passed the filter while the FIFO 0 is full It is cleared by software by writing 1 Bit 3 RF0FF 0x0 rw1c Receive FIFO 0 full flag 0 Receive FIFO 0 is not full 1 Receive FIFO 0 is full Note This bit is set by hardware when ...

Page 413: ... resd Kept at its default value Bit 17 EDZIEN 0x0 rw Enter doze mode interrupt enable 0 Enter sleep mode interrupt disabled 1 Enter sleep mode interrupt enabled Note EDZIF flag bit corresponds to this interrupt An interrupt is generated when both this bit and EDZIF bit are set Bit 16 QDZIEN 0x0 rw Quit doze mode interrupt enable 0 Quit sleep mode interrupt disabled 1 Quit sleep mode interrupt enab...

Page 414: ...RF0OF bit so an interrupt is generated when this bit and RF0OF bit are set Bit 2 RF0FIEN 0x0 rw Receive FIFO 0 full interrupt enable 0 Receive FIFO 0 full interrupt disabled 1 Receive FIFO 0 full interrupt enabled Note The flag bit of this interrupt is the RF0FF bit An interrupt is generated when this bit and RF0FF bit are set Bit 1 RF0MIEN 0x0 rw FIFO 0 receive message interrupt enable 0 FIFO 0 r...

Page 415: ...timing register CAN_BTMG Bit Register Reset value Type Description Bit 31 LOEN 0x0 rw Listen Only mode 0 Listen Only mode disabled 1 Listen Only mode enabled Bit 30 LBEN 0x0 rw Loop back mode 0 Loop back mode disabled 1 Loop back mode enabled Bit 29 26 Reserved 0x0 resd Kept at its default value Bit 25 24 RSAW 0x1 rw Resynchronization width tRSAW tCAN x RSAW 1 0 1 Note This field defines the maxim...

Page 416: ...w Transmit mailbox extended identifier Note This field defines the 18 bit low bytes of the extended identifier Bit 2 TMIDSEL 0xX rw Transmit mailbox identifier type select 0 Standard identifier 1 Extended identifier Bit 1 TMFRSEL 0xX rw Transmit mailbox frame type select 0 Data frame 1 Remote frame Bit 0 TMSR 0x0 rw Transmit mailbox send request 0 No effect 1 Transmit request Note This bit is clea...

Page 417: ...e receive mailbox registers are read only Bit Register Reset value Type Description Bit 31 21 RFSID RFEID 0xXXX ro Receive FIFO standard identifier or receive FIFO extended identifier Note This field defines the 11 bit high bytes of the standard identifier or extended identifier Bit 20 3 RFEID 0xXXXXX ro Receive FIFO extended identifier Note This field defines the 18 bit low bytes of the extended ...

Page 418: ...letely Bit Register Reset value Type Description Bit 31 1 Reserved 0x160E0700 resd Kept at its default value Bit 0 FCS 0x1 rw Filter configuration switch 0 Disabled Filter bank is active 1 Enabled Filter bank is in configuration mode Note The initialization of the filter bank can be configured only when it is in configuration mode 20 7 3 2CAN filter mode configuration register CAN_FMCFG Note This ...

Page 419: ...orresponds to a filter bank 0 Disabled 1 Enabled 20 7 3 6CAN filter bank i filter bit register CAN_ FiFBx i 0 13 x 1 2 Note There are 14 filter banks i 0 13 Each filter bank consists of two 32 bit registers CAN_FiFB 2 1 This register can be modified only when the FAENx bit of the CAN_FACFG register is cleared or the FCS bit of the CAN_FCTRL register is set Bit Register Reset value Type Description...

Page 420: ...functional description Two independent OTGFS modules are embedded in the device The OTGFS module consists of an OTGFS controller PHY and 1280 byte SRAM The OTGFS supports control transfer bulk transfer interrupt transfer and synchronous transfer The OTGFS is a USB full speed dual role device controller The status of the ID line determines whether the OTGFS acts as a host or device When the ID line...

Page 421: ...see CRM_CFG register can be divided to 48MHz Note The APB clock frequency must be greater than 30MHz when OTGFS is enabled 21 3 2 OTGFS pin configuration When the USB module is enabled in the CRM PA11 and PA12 can be multiplexed as DP DM PA8 can be multiplexed as SOF output and configured as a push pull multiplexed output feature The OTGFS input output pins are multiplexed with GPIOs The GPIOs are...

Page 422: ... Host All Channels Interrupt Mask Register Host Channels Interrupt Mask Registers 0 15 Global Interrupt Mask Bit 0 CORE Interrupt AHB Configuration Register OR AND Device All Endpoints Interrupt Register Interrupt source Core interruput register Note Because an interrupt mask only masks an interrupt software must clear an interrupt before unmasking it to avoid servicing an old interrupt 1 7 1 6 1 ...

Page 423: ...FIFO to receive one SETUP Packet on control endpoint The controller does not use these locations which are reserved for SETUP packets One WORD is to be reserved for global OUT NAK Status information is written to the FIFO along with each received packet Therefore a minimum space of largest packet size 4 1 must be allocated to receive data packets In most cases two largest packet size 4 1 spaces ar...

Page 424: ...eshing operation to ensure normal FIFO running Refer to Section Refresh controller transmit FIFO for more information 1 Receive FIFO SRAM allocation Status information is written to the FIFO along with each received packet Therefore a minimum space of largest packet size 4 2 must be allocated to receive data packets If more synchronous endpoints are enabled then at least two largest packet size 4 ...

Page 425: ... has been cleared write 0x1 to the OTGFS_DCTL SGNPINNAK register When the NACK valid interrupt is set it means that the controller does not read FIFO Wait until GINNAKEFF 0x1 in the OTGFS_GINTSTS register indicating that the NAK configuration has taken effect for all IN endpoints Poll the OTGFS_GRSTCTL register and wait until AHBIDLE 1 AHBIDLE H indicates that the controller does not write the FIF...

Page 426: ...nable bit until the application is ready for packet transfer or reception 21 5 3 3 Halting a channel The application can disable a channel by writing 0x1 to the CHDIS and CHENA bits in the OTGFS_HCCHARx register This enables the host to refresh the summited requests if any and generates a channel halted interrupt The application cannot re allocate channels for other transactions until an interrupt...

Page 427: ... non periodic request queue before starting to write to the transmit FIFO The application must always write to the transmit FIFO in WORDs If the packet size is not aligned with WORD the application must use padding The OTGFS host determines the actual packet size according to the programmed maximum packet size and transfer size Figure 21 3 Writing the transmit FIFO Wait for GAHBCFG NPTXFEMPLVL or ...

Page 428: ...es a babble interrupt When the OTGFS controller detects a port babble it flushes the receive FIFO and disables the port Then the controller generates a Port disable interrupt Once receiving the interrupt the application must determine that this is not caused by an overcurrent condition another cause of the port disable interrupt by checking the PRTOVRCACT bit in the OTGFS_HPRT register then perfor...

Page 429: ... Reload 5 New HFIR Value 6 SOF back in Synchronization 400 450 The sequence of operation is as follows 1 After power on reset the current HFIR value set by the application is shown 2 The application loads a new value into the HFIR register 3 The HFIR downcounter is reloaded so it will immediately restart counting to cause SOF synchronization loss 4 Restart HFIR counter 5 The HFIR register receives...

Page 430: ...eration Refer to channel 2 ch_2 for more information The assumptions are as follows The application is attempting to receive two largest packet size packets transfer size is 64 bytes The receive FIFO contains at least one largest packet size packet and two status WORDs per each packet 72 bytes for full speed transfer The non periodic request queue depth is 4 1 Operation process for common bulk and...

Page 431: ...tus is written to the receive FIFO 11 Read and ignore the receive packet status 12 The controller generates a CHHLTD interrupt as soon as the halt status is read from the receive FIFO 13 In response to the CHHLTD interrupt the processor does not allocate the channel for other transfers 2 Handling interrupts The following code describes the interrupt service routine related to the channel during bu...

Page 432: ...store two packets 128 bytes for full speed transfer The non periodic request queue depth is 4 1 OUT SETUP operation process for common bulk and control transfer The sequence of operations shown in Figure 21 7 is as follows 1 Initialize channel 1 according to OTGFS channel initialization requirements 2 Write the first packet for channel 1 3 Along with the last WORD write the controller writes a req...

Page 433: ...sume that this queue can hold 4 entries De allocate ch_1 DATA1 MPS DATA1 write_tx_fifo ch_1 5 set_ch_en ch_2 set_ch_en ch_2 set_ch_en ch_2 read_rx_stsre ad_rx_fifo De allocate ch_2 11 13 1 MPS ch_1 ch_2 ch_2 ch_2 RXFLVL interrupt CHHLTD interrupt XFERCOMPL interrupt 6 12 10 1 MPS XFERCOMPL interrupt 4 2 Handling interrupts The following code describes the interrupt service routine related to the c...

Page 434: ...nterrupt IN transfers Figure 21 8 shows the operation process of a typical interrupt IN transfer Refer to channel 2 ch_2 The assumptions are as follows The application is attempting to receive one largest packet size packet transfer size is 64 bytes from an odd frame The receive FIFO can store at least one largest packet size packet and two status WORDs per packet 1031 bytes for full speed transfe...

Page 435: ...rrupt as soon as the receive packet is read 9 To handle the XFERC interrupt read the PKTCN bit in the OTGFS_HCTSIZ2 register If the PKTCNT bit in the OTGFS_HCTSIZ2 is not equal to 0 disable the channel before re initializing the channel for the next transfer If PKTCNT 0 in the OTGFS_HCTSIZ2 register re initialize the channel for the next transfer In this case the application must reset the ODDFRM ...

Page 436: ...ize packet transfer size is 64 bytes to every frame The periodic transmit FIFO can store one packet 1KB bytes for full speed transfer The periodic request queue depth is 4 1 Common interrupt IN operation process The sequence of operations shown in Figure 21 8 channel 1 is as follows 1 Initialize channel 1 according to OTGFS channel initialization requirements The application must set the ODDFRM bi...

Page 437: ...HB Host USB Device DATA0 MPS DATA0 Periodic Request Queue Assume that this queue can hold 4 entries RXFLVL interrupt write_tx_fifo ch_1 init_reg ch_1 write_tx_fifo ch_1 init_reg ch_1 3 1 MPS 1 MPS DATA1 MPS DATA1 Odd micro frame Even micro frame The following code describes the interrupt service routine related to the channel during interrupt OUT transfers Unmask NAK XACTERR STALL XFERC FRMOVRUN i...

Page 438: ... packet 1031 bytes for full speed transfer The periodic request queue depth is 4 1 Common interrupt IN operation process The sequence of operations shown in Figure 21 9 channel 2 is as follows 1 Initialize channel 2 according to OTGFS channel initialization requirements The application must set the ODDFRM bit in the OTGFS_HCCHAR2 register 2 Set the CHENA bit in the OTGFS_HCCHAR2 register to write ...

Page 439: ...ous IN transfers Unmask XACTERR XFERC FRMOVRUN BBLERR if XFERC or FRMOVRUN if XFERC and HCTSIZx PKTCNT 0 Reset Error Count De allocate Channel else Unmask CHHLTD Disable Channel else if XACTERR or BBLERR Increment Error Count Unmask CHHLTD Disable Channel else if CHHLTD Mask CHHLTD if Transfer Done or Error_count 3 De allocate Channel else Re initialize Channel 21 5 3 12 Initialize synchronous OUT...

Page 440: ...s an example of common synchronous OUT transfers Figure 21 10 Example of common synchronous OUT IN transfers set_ch_en ch_2 set_ch_en ch_2 read_rx_sts read_rx_fifo read_rx_sts init_reg ch_2 init_reg ch_2 write_tx_fifo ch_1 init_reg ch_1 1 1 2 2 6 6 7 9 3 4 ch_1 ch_2 4 5 5 ch_1 ch_2 8 1 MPS 1 MPS XFERC interrupt XFERC interrupt RXFLVL interrupt XFERC interrupt Application AHB Host USB Device DATA0 ...

Page 441: ... Endpoint initialization on enumeration completion At this time the device is ready to accept SOF packets and perform control transfers on control endpoint 0 21 5 4 2Endpoint initialization on USB reset This section describes the operations required for the application to perform when a USB reset signal is detected 1 Set the NAB bit for all OUT endpoints OTGFS_DOEPCTLx SNAK 0x1 for all OUT endpoin...

Page 442: ...application to perform when the application receives a SetConfiguration SetInterface command in a SETUP packet When a SetConfiguration command is received the application must program the endpoint registers according to the characteristics of the valid endpoints defined in the new configuration When a SetInterface command is received the application must program the endpoint registers of the endpo...

Page 443: ... set in the OTGFS_DOEPINTx register during the last OUT transfer it indicates the end of data OUT stage of control transfer 5 Once the completion of data OUT stage the application must perform the following steps If the application needs to transfer a new SETUP packet it must re enable control OUT endpoints refer to OUT data transfers OTGFS_DOEPCTLx EPENA 0x1 To execute the received SETUP commands...

Page 444: ...es the last SETUP packet received before the generation of the SETUP interrupt If the SETUP packet indicates two level control commands the application must perform the following steps Set OTGFS_DOEPCTLx EPENA 0x1 The application must program the registers in the controller to perform the received SETUP commands 3 For status IN stage the application must program the registers based on Non periodic...

Page 445: ...due to the RXFLVL bit in the OTGFS_GINTSTS register Reading an empty receive FIFO will result in unexpected behavior Figure 21 10 shows a flowchart Figure 21 11 Read receive FIFO Frame transfer completed rd_data BCNT 0 wait until GINSTS RXFLVL mem 0 dword_cnt 1 rd_rxfifo rd_data EPNU M dword_cnt Y rd_data rd_reg GRXSTSP N dword_cnt B CNT 11 2 B CNT 1 BCNT 0 rcv_out_pkt packet store in memory 21 5 ...

Page 446: ...re is available space in the receive FIFO irrespective of the NAK and Stall bits on the control endpoints The controller sets the IN NAK and OUT NAK bits for the control IN OUT endpoints on which the SETUP packet was received 2 For every SETUP packet received on the USB line 3 WORDs of data are written to the receive FIFO and the SUPCNT bit is decremented by 1 automatically The first WORD contains...

Page 447: ...t If this condition occurs the OTGFS controller generates an interrupt B2BSTUP bit in the OTGFS_DOEPINTx register 21 5 4 13 IN data transfers This section describes the internal data flow during IN data transfers and how the application handles IN data transfers 1 The application can either select a polling or an interrupt mode In polling mode the application monitors the status of the endpoint tr...

Page 448: ...cket count 0x1 2 If an endpoint is enabled for data transfers the controller updates the Transfer size register At the end of the IN transfer indicated by endpoint disable interrupt bit the application must read the Transfer size register to determine how much data in the transmit FIFO have already been sent on the USB line 3 Data fetched in the transmit FIFO Application programmed initial transfe...

Page 449: ...k or interrupt transfers Application requirements 1 For OUT data transfers the transfer size of the endpoint transfer register must be set to a multiple of the largest packet size for the endpoint and adjusted to the WORD boundary if mps epnum mod 4 0 transfer size epnum n mps epnum WORD Aligned else transfer size epnum n mps epnum 4 mps epnum mod 4 Non WORD Aligned packet count epnum n n 0 2 When...

Page 450: ...ed mode for an OUT endpoint is written to the receive FIFO one of the following conditions The transfer size and packet count are both 0 The last OUT data packet written to the receive FIFO is a short packet 0 data packet size largest packet size 7 When the application pops this entry OUT data transfer complete a transfer completed interrupt is generated and the endpoint enable bit is cleared Appl...

Page 451: ...n the OTGFS_GINTSTS register 4 Upon receiving the packet count of USB packets the controller internally sets the NAK bit for the endpoint to prevent it from receiving any more packets 5 The application processes the interrupt and reads the data from the receive FIFO 6 When the application reads all the data equivalent to XFERSIZE the controller generates an XFERC interrupt in the OTGFS_DOEPINTx re...

Page 452: ... bits Endpoint enable 0x1 CNAK 0x1 Even Odd frame 0x0 Even 0x1 Odd 3 Wait for the RXFLVL interrupt in the OTGFS_GINTSTS register and read all the data packets from the receive FIFO See Read FIFO for more information This step can be repeated several times depending on the transfer size 4 When the XFERC interrupt is set in the OTGFS_DOEPINTx register it indicates the completion of the synchronous O...

Page 453: ...hat of the PKTCNT bit in the OTGFS_DIEPTSIZx register Program the OTGFS_DIEPCTLx register Read the OTGFS_DSTS register to determine the current frame number Program the OTGFS_DIEPCTLx with the maximum packet size MPS bit Set USBACTEP 0x1 in the OTGFS_DIEPCTLx register Set EPTYPE 0x1 in the OTGFS_DIEPCTLx register marking synchronization Set the FIFO number of the endpoint through the TXFNUM bit in...

Page 454: ...ccommodate the complete ISO OUT data packet the controller drops the received ISO OUT data When the synchronous OUT data packet is received with CRC errors When the synchronous OUT token received by the controller is corrupted When the application is very slow in reading the receive FIFO 2 When the controller detects the end of periodic frames before transfer complete to all synchronous OUT endpoi...

Page 455: ...from any synchronous IN endpoint because this can trigger the incomplete synchronous IN interrupt 2 The incomplete synchronous IN transfer interrupt in the OTGFS_GINTSTS register indicates that at least one synchronous IN endpoint is with incomplete synchronous IN transfers 3 The application must read the endpoint control registers of all synchronous IN endpoints to determine which one is with inc...

Page 456: ...enerates an INTKNTXFEMP interrupt A zero length data packet is transmitted on the USB for synchronous IN endpoints An NAK handshake signal is transmitted on the USB for interrupt IN endpoints 5 The packet count for the endpoints is decremented by one under the following conditions For synchronous endpoints when a zero or non zero length data packet is transmitted For interrupt endpoints when an AC...

Page 457: ...s are active in both host and device modes When the OTGFS controller operates in either host or device mode the application must not access the register group from the other mode If an illegal access occurs a mode mismatch interrupt is generated and the MODMIS bit in the OTGFS_GINTSTS register is affected When the controller switches from one mode to the other the registers in the new mode must be...

Page 458: ...e register for power and clock control It is valid in both host and device modes 21 6 2 OTGFS register address map Table 21 4 shows the USB OTG register map and their reset values These peripheral registers must be accessed by words 32 bit Table 21 4 OTGFS register map and reset values Register name Offset Reset value OTGFS_GOTGCTL 0x000 0x0001 0000 OTGFS_GOTGINT 0x004 0x0000 0000 OTGFS_GAHBCFG 0x...

Page 459: ... 0x560 0x0000 0000 OTGFS_HCINT3 0x568 0x0000 0000 OTGFS_HCINTMSK3 0x56C 0x0000 0000 OTGFS_HCTSIZ3 0x570 0x0000 0000 OTGFS_HCCHAR4 0x580 0x0000 0000 OTGFS_HCINT4 0x588 0x0000 0000 OTGFS_HCINTMSK4 0x58C 0x0000 0000 OTGFS_HCTSIZ4 0x590 0x0000 0000 OTGFS_HCCHAR5 0x5A0 0x0000 0000 OTGFS_HCINT5 0x5A8 0x0000 0000 OTGFS_HCINTMSK5 0x5AC 0x0000 0000 OTGFS_HCTSIZ5 0x5B0 0x0000 0000 OTGFS_HCCHAR6 0x5C0 0x0000...

Page 460: ...INT13 0x6A8 0x0000 0000 OTGFS_HCINTMSK13 0x6AC 0x0000 0000 OTGFS_HCTSIZ13 0x6B0 0x0000 0000 OTGFS_HCCHAR14 0x6C0 0x0000 0000 OTGFS_HCINT14 0x6C8 0x0000 0000 OTGFS_HCINTMSK14 0x6CC 0x0000 0000 OTGFS_HCTSIZ14 0x6D0 0x0000 0000 OTGFS_HCCHAR15 0x6E0 0x0000 0000 OTGFS_HCINT15 0x6E8 0x0000 0000 OTGFS_HCINTMSK15 0x6EC 0x0000 0000 OTGFS_HCTSIZ15 0x6F0 0x0000 0000 OTGFS_DCFG 0x800 0x0220 0000 OTGFS_DCTL 0x...

Page 461: ...0x9B0 0x0000 0000 OTGFS_DTXFSTS5 0x9B8 0x0000 0200 OTGFS_DIEPCTL6 0x9C0 0x0000 0000 OTGFS_DIEPINT6 0x9C8 0x0000 0080 OTGFS_DIEPTSIZ6 0x9D0 0x0000 0000 OTGFS_DTXFSTS6 0x9D8 0x0000 0200 OTGFS_DIEPCTL7 0x9E0 0x0000 0000 OTGFS_DIEPINT7 0x9E8 0x0000 0080 OTGFS_DIEPTSIZ7 0x9F0 0x0000 0000 OTGFS_DTXFSTS7 0x9F8 0x0000 0200 OTGFS_DOEPCTL0 0xB00 0x0000 8000 OTGFS_DOEPINT0 0xB08 0x0000 0080 OTGFS_DOEPTSIZ0 0...

Page 462: ...ler is in B device mode Bit 15 0 Reserved 0x0000 resd Kept at its default value 21 6 3 2OTGFS interrupt status control register OTGFS_GOTGINT The application reads this register to know about which kind of OTG interrupt is generated and writes this register to clear the OTG interrupt Bit Register Reset value Type Description Bit 31 3 Reserved 0x0000 resd Kept at its default value Bit 2 SESENDDET 0...

Page 463: ...ription Bit 31 COTXPKT 0x0 rw Accessible in both host mode and device modes Corrupt Tx packet This bit is for debug purpose only Do not set this bit to 1 Bit 30 FDEVMODE 0x0 rw Accessible in both host mode and device modes Force device mode Writing 1 to this bit forces the controller to go into device mode irrespective of the status of the ID input point 0 Normal mode 1 Force device mode After set...

Page 464: ...field indicates the FIFO number that must be refreshed through the TxFIFO Flush bit Do not make changes to this field until the controller clears the TxFIFO Flush bit 00000 Non periodic TxFIFO in host mode Tx FIFO 0 in device mode 00001 Periodic TxFIFO in host mode TXFIFO 1 in device mode 00010 TXFIFO 2 in device mode 01111 TXFIFO 15 in device mode 10000 Refresh all the transmit FIFOs in device or...

Page 465: ...s is can be cleared automatically the controller this clear this bit after all the necessary logic is reset in the controller Bit 0 CSFTRST 0x0 rw1s Accessible in both host mode and device modes Controller soft reset Resets the hclk and phy_clock domain as follows Clears all interrupts and CSR registers except for the following bits HCFG FSLSPCS DCFG DECSPD DCTL SFTDIS Resets all state machines ex...

Page 466: ...n connector ID status Bit 27 Reserved 0x0 resd Kept at its default value Bit 26 PTXFEMP 0x1 ro Accessible in host mode only Periodic TxFIFO Empty The interrupt is generated when the Periodic Transmit FIFO is either half or completely empty and there is space for a request to be written in the periodic request queue The half or completely empty status depends on the periodic transmit FIFO empty lev...

Page 467: ...e All Endpoints Interrupt register to determine the exact number of the IN endpoint on which the interrupt occurred and then read the corresponding Device IN Endpoint n Interrupt register to determine the exact source of the interrupt The application must clear the corresponding status bit in the corresponding Device IN Endpoint n Interrupt register to clear this bit Bit 17 16 Reserved 0x0 resd Ke...

Page 468: ...Level bit in the Core AHB Configuration register Bit 4 RXFLVL 0x0 ro Accessible in both host and device modes RxFIFO Non Empty Indicates that there is at least one packet to be read from the receive FIFO Bit 3 SOF 0x0 rw1c Accessible in both host and device modes Start of Frame In host mode the controller sets this bit to indicate that an SOF full speed or Keep Alive low speed is transmitted on th...

Page 469: ...ONINTMSK 0x0 rw Accessible in both host and device modes Disconnect detected interrupt mask Bit 28 CONIDSCHGMSK 0x0 rw Accessible in both host and device modes Connector ID status change mask Bit 27 Reserved 0x0 resd Kept at its default value Bit 26 PTXFEMPMSK 0x0 rw Accessible in host mode only Periodic TxFIFO empty mask Bit 25 HCHINTMSK 0x0 rw Accessible in host mode only Host channels interrupt...

Page 470: ...he Receive FIFO The receive status contents are interpreted differently in host and device modes Then controller ignores the receive status pop read when the receive FIFO is empty and returns the value of 0x0000 0000 The application can only pop the receive status FIFO when the receive FIFO non empty bit of the Core Interrupt register is set Host mode Bit Register Reset value Type Description Bit ...

Page 471: ...RxFIFO Depth This value is in terms of 32 bit words Minimum value is 16 Maximum value is 512 The power on reset value of this register is defined as the largest receive data FIFO depth during the configuration 21 6 3 10 OTGFS non periodic Tx FIFO size OTGFS_GNPTXFSIZ Endpoint 0 Tx FIFO size registers OTGFS_DIEPTXF0 The application can program the SRAM size and start address of the non periodic tra...

Page 472: ...rved Reset value Configurable Bit 15 0 NPTXFSPCAVAIL 0x0200 ro Non periodic TxFIFO space available Indicates the amount of space available in the non periodic TxFIFO Values are in terms of 32 bit words 00 Non periodic transmit FIFO is full 01 1 location available 02 2 locations available N n locations available 0 n 256 Others Reserved Reset value Configurable 21 6 3 12 OTGFS general controller con...

Page 473: ...edly for instantiated IN endpoint FIFO1 15 The GNPTXFSIZ register is used to program the depth and memory start address of the IN endpoint FIFO 0 Bit Register Reset value Type Description Bit 31 16 INEPTXFDEP 0x0200 ro rw IN Endpoint TxFIFO depth Values are in terms of 32 bit words Minimum value is 16 Maximum value is 512 The reset value is the maximum possible IN endpoint transmit FIFO depth Bit ...

Page 474: ...l speed The number of PHY locks in this field indicates the frame interval The application can write a value to the host frame interval register only after the port enable bit in the host port control and status register has been set If no value is programmed the controller calculates the value based on the PHY clock frequency defined in the FS LS PHY clock select bit of the host configuration reg...

Page 475: ...mber of free space available to be written in the periodic transmit FIFO in terms of 32 bit words 0000 Periodic transmit FIFO is full 0001 1 space available 0010 2 space available N n space available 0 n 512 Others Reserved 21 6 4 5OTGFS host all channels interrupt register OTGFS_HAINT When a flag event occurs on a channel the host all channels interrupt register interrupts the application through...

Page 476: ...bit to control power supply to this port by writing 1 or 0 0 Power off 1 Power on Note This bit is not associated with interfaces The application must follow the programming manual to set this bit for various interfaces Bit 11 10 PRTLNSTS 0x0 ro Port line status Indicates the current logic status of the USB data lines Bit 10 Logic level of D Bit 11 Logic level of D Bit 9 Reserved 0x0 resd Kept at ...

Page 477: ... No overcurrent 1 Overcurrent condition Bit 3 PRTENCHNG 0x0 rw1c Port enable disable change The controller sets this bit when the status of the port enable bit 2 in this register changes This bit can only be set by the controller The application must write 1 to clear this bit Bit 2 PRTENA 0x0 rw1c Port enable A port is enabled only by the controller after a reset sequence This port is enabled by a...

Page 478: ...ndicates whether the transfer is in IN or OUT 0 OUT 1 IN Bit 14 11 EPTNUM 0x0 rw Endpoint number Indicates the endpoint number on the device serving as data source or receiver Bit 10 0 MPS 0x000 rw Maximum packet size Indicates the maximum packet size of the corresponding port 21 6 4 9OTGFS host channelx interrupt register OTGFS_HCINTx x 0 15 where x channel number This register contains the statu...

Page 479: ...e channels described in the previous section Bit Register Reset value Type Description Bit 31 11 Reserved 0x000000 resd Kept at its default value Bit 10 DTGLERRMSK 0x0 rw Data toggle error mask Bit 9 FRMOVRUNMSK 0x0 rw Frame overrun mask Bit 8 BBLERRMSK 0x0 rw Babble error mask Bit 7 XACTERRMSK 0x0 rw Transaction error mask Bit 6 NYETMSK 0x0 rw NYET response received interrupt mask Bit 5 ACKMSK 0x...

Page 480: ... interval 10 90 of the frame interval 11 95 of the frame interval Bit 10 4 DEVADDR 0x00 rw Device address The application must program this field every time a SetAddress command is received Bit 3 Reserved 0x0 resd Kept at its default value Bit 2 NZSTSOUTHSHK 0x0 rw Non zero length status OUT handshake The application can use this field to select the handshake the controller sends on receiving a no...

Page 481: ...nds a NAK handshake on all packets except on SETUP transfers Drops all synchronous OUT packets Bit 2 GNPINNAKSTS 0x0 ro Global Non periodic IN NAK status 0 A handshake is sent based on the data status in the transmit FIFO 1 A NAK handshake is sent on all non periodic IN endpoints irrespective of the data status in the transmit FIFO Bit 1 SFTDISCON 0x1 rw Software disconnect The application uses th...

Page 482: ... an erratic error the application can only perform a software disconnect recover Bit 2 1 ENUMSPD 0x0 ro Enumerated speed Indicates the speed at which the controller has determined after speed detection through a sequence 01 Reserved 10 Reserved 11 Full speed PHY clock is running at 48MHz Others Reserved Bit 0 SUSPSTS 0x0 ro Suspend status In device mode this bit is set as long as a suspend conditi...

Page 483: ...ate an OUT endpoint interrupt Each of the bits in the OTGFS_DOEPINTx registers can be masked by writing to the register All interrupts are masked by default Bit Register Reset value Type Description Bit 31 10 Reserved 0x000000 resd Kept at its default value Bit 9 BNAOUTMSK 0x0 rw BNA interrupt mask 0 Interrupt masked 1 Interrupt unmasked Bit 8 OUTPERRMSK 0x0 rw OUT packet error mask 0 Interrupt ma...

Page 484: ...pt register corresponding to this interrupt is still set Bit Register Reset value Type Description Bit 31 24 Reserved 0x0000 resd Kept at its default value Bit 23 16 OUTEPTMSK 0x0000 rw OUT EP interrupt mask bits One OUT endpoint per bit Bit 16 for OUT endpoint 0 bit 18 for OUT endpoint 2 0 Interrupt masked 1 Interrupt unmasked Bit 15 8 Reserved 0x0000 resd Kept at its default value Bit 7 0 INEPTM...

Page 485: ...lears this bit when a SETUP token is received If a NAK bit a global non periodic IN NAK or global OUT NAK bit is set along with this bit the STALL bit has priority Bit 20 Reserved 0x0 resd Kept at its default value Bit 19 18 EPTYPE 0x0 ro Endpoint type Set to 0 by hardware for control endpoints Bit 17 NAKSTS 0x0 ro NAK status Indicates the following 0 The controller is transmitting non NAK handsha...

Page 486: ...e 0 Disabled Set DATA1 PID disabled or Do not force odd frame 1 Set DATA1 PID enabled or forced odd frame Bit 28 SETD0PID SETEVENFR 0x0 rw Set DATA0 PID Applies to interrupt bulk IN endpoints only Writing to this bit sets the endpoint data PID bit in this register to DATA0 Set Even frame Applies to synchronous IN endpoints only Writing to this bit sets the Even Odd frame to even frame 0 Disabled S...

Page 487: ...ata PID Applies to interrupt bulk IN endpoints only This bit contains the PID of the packet to be transmitted on this endpoint The application must program the PID of the initial data packet to be received or transmitted on this endpoint after the endpoint is enabled The application programs DATA0 or DATA1 PID through the SetD1PID and SetD0PID of this register 0 DATA0 1 DATA1 Even Odd frame Applie...

Page 488: ...P token is received for this endpoint If a NAK bit global non periodic OIT NAK bit is set along with this bit the STALL bit has priority The controller always responds to SETUP data packets regardless of whether this bit is set or not Bit 20 SNP 0x0 rw Snoop mode This bit configures the endpoint to Snoop mode In this mode the controller does not check the correctness of OUT packets before transmit...

Page 489: ...er to DATA1 Set odd frame Applies to synchronous OUT endpoints only Writing to this bit sets the Even Odd frame to odd frame 0 Disabled Set DATA1 PID disabled or Do not force odd frame 1 Set DATA1 PID enabled or forced odd frame Bit 28 SETD0PID SETEVENFR 0x0 rw Set DATA0 PID Applies to interrupt bulk OUT endpoints only Writing to this bit sets the endpoint data PID bit in this register to DATA0 Se...

Page 490: ...ether this bit is set or not Bit 16 DPID EOFRNUM 0x0 ro Endpoint data PID Applies to interrupt bulk OUT endpoints only This bit contains the PID of the packet to be transmitted on this endpoint The application must program the PID of the initial data packet to be received or transmitted on this endpoint after the endpoint is enabled The application programs DATA0 or DATA1 PID through the SetD1PID ...

Page 491: ...associated transmit FIFO periodic or non periodic was empty An interrupt is generated on the endpoint for which an IN token was received Bit 3 TIMEOUT 0x0 rw1c Timeout condition Applies to control IN endpoints only This bit indicates that the controller has detected a timeout condition for the last IN token on this endpoint Bit 2 Reserved 0x0 resd Kept at its default value Bit 1 EPTDISD 0x0 rw1c E...

Page 492: ...cket Bit 18 7 Reserved 0x000 resd Kept at its default value Bit 6 0 XFERSIZE 0x00 rw Transfer size Indicates the transfer size in bytes for the endpoint 0 The controller interrupts the application when the transfer size becomes 0 The transfer size can be set to the maximum packet size of the endpoint at the end of each packet The controller decrements this field every time a packet from the extern...

Page 493: ... Packet count Indicates the total number of USB packets data transfer size on the endpoint this field is decremented every time a packet is read from the transmit FIFO maximum packet size and short packet Bit 18 0 XFERSIZE 0x00000 rw Transfer Size Indicates the transfer size in bytes for the current endpoint The controller interrupts the application when the transfer size becomes 0 The transfer si...

Page 494: ... packets transmitted on the endpoint This field is decremented every time a packet is written to the receive FIFO maximum packet size and short packet Bit 18 0 XFERSIZE 0x00000 rw Transfer size Indicates the transfer size in bytes for the current endpoint The controller interrupts the application when the transfer size becomes 0 The transfer size can be set to the maximum packet size of the endpoi...

Page 495: ...s coarse calibration and fine calibration 22 3Interrupt requests Table 22 1 ACC interrupt requests Interrupt event Event flag Enable bit Calibration ready CALRDY CALRDYIEN Reference signal lost RSLOST EIEN ACC interrupt events are linked to the same interrupt vector see Figure 25 1 Interrupt events include During calibration process When the calibration gets ready or reference signal lost occurs t...

Page 496: ... USB_SOF USB Start of Frame signal given by the USB device Its high level width is 12 system clock cycles a pulse signal of 1 ms HICKCLK HICK clock The original HICK output frequency is 48MHz but the sampling clock used by the HICK calibration module is frequency divider 1 6 clock about 8MHz HICKCAL HICK module calibration signal For the HICK clock after frequency division 1 6 the HICK clock frequ...

Page 497: ...re 22 3 Cross return algorithm C1 7980 C3 8020 C2 8000 From the above figure auto calibration function will adjust the HICKCAL or HICKTRIM according to the specified step as soon as the condition for triggering auto calibration is reached Cross If the auto calibration condition is met the actual sampling data in the first 1ms period will be either less than C2 or greater than C2 When this value is...

Page 498: ...he rising edge the CANLON the auto calibration module can also be activated so that the HICK frequency can be adjusted to be within a range of 0 5 steps of the center frequency as soon as the CANLON is enabled Under one of the above mentioned circumstances the HICK frequency can be calibrated to be within 0 5 steps of the center frequency To achieve the best calibration accuracy it is recommended ...

Page 499: ...se or decrease by 40KHz design value This is a positive relationship While ENTRIM 1 only the HICKTRIM is calibrated If the step is incremented or decremented by one the HICKTRIM will be incremented or decremented by one accordingly and the HICK frequency will increase or decrease by 20KHz design value This is a positive relationship Bit 7 6 Reserved 0x0 rw Forced by hardware to 0 Bit 5 CALRDYIEN 0...

Page 500: ...ved 0x0000 resd Forced to 0 by hardware Bit 15 0 C1 0x1F2C rw Compare 1 This value is the lower boundary for triggering calibration and its default value is 7980 When the number of clocks sampled by ACC in 1ms period is less than or equal to C1 auto calibration is triggered automatically When the actual sampling value number of clocks in 1ms is greater than C1 but less than C3 auto calibration is ...

Page 501: ...selects from TMR10_C1OUT USART1 and USART through the IR_SRC_SEL 1 0 bit in the SCFG_CFG1 register while the high frequency carrier signal is provided by the TMR11_C1OUT register The IR_POL bit in the SCFG_CFG1 register controls whether the IR_OUT output is reversed or not The IR_OUT signal is output through multiplexed function via PB9 or PA13 multiplexed mode needs to be configured in advance Fi...

Page 502: ...ings for read and write Multiplexed address data mode Synchronous mode Programmable timing control registers Translate the AHB data size into the appropriate external memory data size NAND has the following features Chip select signal supports 2 external memories 8 bit or 16 bit wide NAND Flash Two storage spaces with programmable timing control registers Translate the AHB data size into the appro...

Page 503: ...rea ping pong access Automatic refresh operation of software programmable refresh rate Supports self refresh mode Supports power down mode SDRAM power on initialization through software CAS latency can be configured 1 2 3 SDRAM clock cycles Cacheable Read FIFO with 6x 32 bit depth ...

Page 504: ...y interface XMC_A 25 0 XMC_D 15 0 XMC_NOE XMC_NWE XMC_NWAIT XMC_NE 4 1 XMC_NADV XMC_LB XMC_UB XMC_CLK XMC_NCE 3 2 XMC_INT 3 2 XMC_NCE4_1 XMC_NCE4_2 XMC_NREG XMC_NIORD XMC_NIOWR XMC_CD XMC_INTR XMC_SDCS0 XMC_SDCKE0 XMC_SDNWE XMC_SDNRAS XMC_SDNCAS XMC_SDCLK XMC_SDCS1 XMC_SDCKE1 While interfacing to the external memory NOR PSRAM NAND PC card and SDRAM uses different pins respectively as shown in Tabl...

Page 505: ...l for general purpose space and attribute XMC_NWE Output Write enable signal for general purpose space XMC_NIORD Output Output enable signal for IO space XMC_NIOWR Output Write enable signal for IO space XMC_NREG Output Attribute space select signal XMC_D 15 0 Read input write output Data bus XMC_CD Input PC card detection signal active high XMC_NWAIT Input Ready Busy R B XMC_INTR Input PC card in...

Page 506: ...h 6FFF FFFFh XMC_NE 4 NAND bank2 regular memory 128 MB 7000 0000h 77FF FFFFh NAND bank2 special memory 128 MB 7800 0000h 7FFF FFFFh XMC_NCE 2 NAND bank3 regular memory 128 MB 8000 0000h 87FF FFFFh NAND bank3 special memory 128 MB 8800 0000h 8FFF FFFFh XMC_NCE 3 PC card common memory 32 MB A800 0000h A9FF FFFFh PC card attribute memory 32 MB AC00 0000h ADFF FFFFh PC card I O memory 32 MB AE00 0000h...

Page 507: ...ttribute memory space 11 I O space HADDR 31 28 HADDR 26 0 1100 SDRAM BANK1 BANK and row column address mapping HADDR 31 28 HADDR 26 0 1101 SDRAM BANK2 BANK and row column address mapping Table 24 6 8 bit SDRAM address mapping Row size HADDR AHB internal address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11 bit Reserved Bank 1 0 Row 10 0 Column 7 0 Reserved Bank ...

Page 508: ...ion Pin signals vary from external memory to external memory Table 24 8 lists typical pin signals Table 24 8 Pin signals for NOR and PSRAM XMC pin name NOR Flash PSRAM XMC_CLK Clock synchronous mode Clock synchronous mode XMC_NE x Chip select Chip select XMC_NADV Address latch or address valid Address latch or address valid XMC_A 23 16 XMC_A 0 Address bus Address bus XMC_NOE Output enable Output e...

Page 509: ...nous read write 8 16 32 8 One time access or split into 2 or 4 accesses Asynchronous read write 8 16 32 16 XMC_LB and XMC_UB One time or split into two access NOR Flash Asynchronous read 8 16 Asynchronous read write 16 16 Asynchronous read write 32 16 Split into 2 XMC accesses Synchronous read 16 16 Synchronous read 32 16 Split into 2 XMC accesses PSRAM Asynchronous read 8 16 Asynchronous write 8 ...

Page 510: ... CRPGS CRAM page size 0x0 Bit 15 NWASEN NWAIT in asynchronous transfer enable Configure according to memory specifications Bit 14 RWTD Read write timing different 0x0 Bit 13 NWSEN NWAIT in synchronous transfer enable 0x0 Bit 12 WEN Write enable Configure according to needs Bit 11 NWTCFG NWAIT timing configuration 0x0 Bit 10 WRAPEN Wrapped enable 0x0 Bit 9 NWPOL NWAIT polarity Configure according t...

Page 511: ...from XMC ADDRST 1 HCLK DTST 1 HCLK High High Z Memory address Don t care Address signals Data signals Chip select signal XMC_LB XMC_UB Mode 2 As configured in Table 24 14 and Table 24 15 the XMC uses mode 2 to access the external memory The timing of read operation is shown in Figure 24 5 The timing of write operation is shown in Figure 24 6 Table 24 14 Mode 2 SRAM NOR Flash chip select control re...

Page 512: ... NOR Flash chip select timing register Bit Description Configuration Bit 31 30 Reserved 0x0 Bit 29 28 ASYNCM Asynchronous mode 0x0 Bit 27 24 DTLAT Data latency 0x0 Bit 23 20 CLKPSC Clock prescale 0x0 Bit 19 16 BUSLAT Bus latency Indicates the time the XMC_NE x from the rising edge to the falling edge Configure according to needs and memory specifications Bit 15 8 DTST Data setup time Refer to Figu...

Page 513: ...ing of write operation is shown in Figure 24 8 Table 24 16 Mode A SRAM NOR Flash chip select control register Bit Description Configuration Bit 31 20 Reserved 0x0 Bit 19 MWMC Memory write mode control 0x0 Bit 18 16 CRPGS CRAM page size 0x0 Bit 15 NWASEN NWAIT in asynchronous transfer enable Configure according to memory specifications Bit 14 RWTD Read write timing different 0x1 Bit 13 NWSEN NWAIT ...

Page 514: ...d memory specifications Table 24 18 Mode A SRAM NOR Flash write timing register Bit Description Configuration Bit 31 30 Reserved 0x0 Bit 29 28 ASYNCM Asynchronous mode 0x0 Mode A Bit 27 20 Reserved 0x0 Bit 19 16 BUSLAT Bus latency Indicates the time the XMC_NE x from the rising edge to the falling edge Configure according to needs and memory specifications Bit 15 8 DTST Data setup time Refer to Fi...

Page 515: ...Bit 31 20 Reserved 0x0 Bit 19 MWMC Memory write mode control 0x0 Bit 18 16 CRPGS CRAM page size 0x0 Bit 15 NWASEN NWAIT in asynchronous transfer enable Configure according to memory specifications Bit 14 RWTD Read write timing different 0x1 Bit 13 NWSEN NWAIT in synchronous transfer enable 0x0 Bit 12 WEN Write enable Configure according to needs Bit 11 NWTCFG NWAIT timing configuration 0x0 Bit 10 ...

Page 516: ... memory specifications Table 24 21 Mode B SRAM NOR Flash write timing register Bit Description Configuration Bit 31 30 Reserved 0x0 Bit 29 28 ASYNCM Asynchronous mode 0x1 Mode B Bit 27 20 Reserved 0x0 Bit 19 16 BUSLAT Bus latency Indicates the time the XMC_NE x from the rising edge to the falling edge Configure according to needs and memory specifications Bit 15 8 DTST Data setup time Refer to Fig...

Page 517: ... Bit 31 20 Reserved 0x0 Bit 19 MWMC Memory write mode control 0x0 Bit 18 16 CRPGS CRAM page size 0x0 Bit 15 NWASEN NWAIT in asynchronous transfer enable Configure according to memory specifications Bit 14 RWTD Read write timing different 0x1 Bit 13 NWSEN NWAIT in synchronous transfer enable 0x0 Bit 12 WEN Write enable Configure according to needs Bit 11 NWTCFG NWAIT timing configuration 0x0 Bit 10...

Page 518: ...ory specifications Table 24 24 Mode C SRAM NOR Flash write timing register Bit Description Configuration Bit 31 30 Reserved 0x0 Bit 29 28 ASYNCM Asynchronous mode 0x1 Mode C Bit 27 20 Reserved 0x0 Bit 19 16 BUSLAT Bus latency Indicates the time the XMC_NE x from the rising edge to the falling edge Configure according to needs and memory specifications Bit 15 8 DTST Data setup time Refer to Figure ...

Page 519: ...d 0x0 Bit 19 MWMC Memory write mode control 0x0 Bit 18 16 CRPGS CRAM page size 0x0 Bit 15 NWASEN NWAIT in asynchronous transfer enable Configure according to memory specifications Bit 14 RWTD Read write timing different 0x1 Bit 13 NWSEN NWAIT in synchronous transfer enable 0x0 Bit 12 WEN Write enable Configure according to needs Bit 11 NWTCFG NWAIT timing configuration 0x0 Bit 10 WRAPEN Wrapped en...

Page 520: ... specifications Table 24 27 Mode D SRAM NOR Flash write timing register Bit Description Configuration Bit 31 30 Reserved 0x0 Bit 29 28 ASYNCM Asynchronous mode 0x3 Mode D Bit 27 20 Reserved 0x0 Bit 19 16 BUSLAT Bus latency Indicates the time the XMC_NE x from the rising edge to the falling edge Configure according to needs and memory specifications Bit 15 8 DTST Data setup time Refer to Figure 24 ...

Page 521: ...MWMC Memory write mode control 0x0 Bit 18 16 CRPGS CRAM page size 0x0 Bit 15 NWASEN NWAIT in asynchronous transfer enable Configure according to memory specifications Bit 14 RWTD Read write timing different 0x0 Bit 13 NWSEN NWAIT in synchronous transfer enable 0x0 Bit 12 WEN Write enable Configure according to needs Bit 11 NWTCFG NWAIT timing configuration 0x0 Bit 10 WRAPEN Wrapped enable 0x0 Bit ...

Page 522: ...o Figure 24 15 and Figure 24 16 Configure according to needs and memory specifications Bit 7 4 ADDRHT Address hold time Refer to Figure 24 15 and Figure 24 16 Configure according to needs and memory specifications Bit 3 0 ADDRST Address setup time Refer to Figure 24 15 and Figure 24 16 Configure according to needs and memory specifications Figure 24 15 NOR PSRAM multiplexed mode read access XMC_A ...

Page 523: ...les of XMC waiting in the next cycle of XMC_NWAIT signal NWTCFG 0 Table 24 30 Synchronous mode SRAM NOR Flash chip select control register Bit Description Configuration Bit 31 20 Reserved 0x0 Bit 19 MWMC Memory write mode control 0x1 Bit 18 16 CRPGS CRAM page size Configure according to memory specifications Bit 15 NWASEN NWAIT in asynchronous transfer enable 0x0 Bit 14 RWTD Read write timing diff...

Page 524: ...e 24 18 Bit 19 16 BUSLAT Bus latency Indicates the time the XMC_NE x from the rising edge to the falling edge Configure according to needs and memory specifications Bit 15 8 DTST Data setup time 0x0 Bit 7 4 ADDRHT Address hold time 0x0 Bit 3 0 ADDRST Address setup time 0x0 Figure 24 17 NOR PSRAM synchronous multiplexed mode read access XMC_A 25 16 XMC_LB XMC_UB XMC_NE x XMC_D 15 0 High Z Memory ad...

Page 525: ...C pin name 8 bit NAND Flash 16 bit NAND Flash XMC_NCE 2 Chip select Chip select XMC_A 17 Address latch enable ALE Address latch enable ALE XMC_A 16 Command latch enable CLE Command latch enable CLE XMC_NOE Output enable NRE Output enable NRE XMC_NWE Write enable Write enable XMC_D 15 0 Data bus Do not use XMC_D 15 8 Use XMC_D 7 0 as data bus XMC_NWAIT Ready Busy R B Ready Busy R B Access address T...

Page 526: ...s during which the data bus is kept in high Z state W HCLK cycle RGST SPST Memory set up time R W HCLK cycle RGWT SPWT Memory set up time R W HCLK cycle RGHT SPHT Memory set up time R W HCLK cycle Figure 24 19 NAND read access XMC_A 17 16 XMC_NCE 2 XMC_D 15 0 High Z RGDHIZT 1 HCLK ALE CLE Chip select signal Data from XMC XMC_NWE XMC_NOE High RGST 2 HCLK RGWT 1 HCLK RGHT HCLK NRE Data signals XMC_D...

Page 527: ...the XMC_BK2ECC register To perform an ECC computation 1 Configure the ECCPGS bit to select the number of bytes to be computed by ECC module 256 512 1024 2048 4096 or 8192 bytes 2 Enable the ECCEN bit 3 Read write from and to the data section 4 After receiving sending the same number of bytes as the value programed in the ECCPGS the XMC will store the ECC computed value into the XMC_BK2ECC register...

Page 528: ...according to the HADDR bit In case that the AHB data width is not equal to that of the memories the XMC will make appropriate arrangement according to the typical signals of the external memories Table 24 37 lists the operation modes supported by XMC Table 24 37 Access data width and PC card data width Memory Mode AHB data size Memory data size Description PC card Read Write 8 16 Use XMC_NCE4_1 Re...

Page 529: ...icable to both devices 1 Program the SDRAM_CTRLx register according to the external SDRAM device row column and bus width and the number of BANK Read and write operations from to the SDRAM must be also programmed into the SDRAM_CTRLx register 2 Program the memory device timing into the SDRAM_TMx register The TRP and TRC timings must be programmed into the SDRAM_TM1 register 3 Set CMD 001 to start ...

Page 530: ...er active row the write operation is performed If the next write access targets an inactive row the SDRAM controller generates a precharge command The BANK where the inactive row is has other open rows if no other rows the precharge is unnecessary and activates the new row and initiates a write operation Figure 24 22 SDRAM write access waveforms Trcd 2 9 consecutive write access XMC_ SDCS XMC_ A 1...

Page 531: ...troller precharges the currently active row in order to disable the current row activates a new row and starts a read write command to a new row If the next access is sequential and the current access crosses BANK boundary two cases are possible If the current BANK is not the last one the SDRAM will perform access to the next BANK If the next BANK is an active row and the active row matches the on...

Page 532: ...mode by setting CMD 000 or by read write access to the SDRAM Power down mode This mode is selected by setting CMD 110 and by configuring the Target Bank bits BK1 and or BK2 in the SDRAM_CMD register During power down mode the SDRAM device can also perform auto refresh operation When an auto refresh command occurs the SDRAM exists from the power down mode before performing auto refresh operation Af...

Page 533: ...ts default value Bit 19 MWMC 0x0 rw Memory write mode control 0 Write operations are performed in asynchronous mode 1 Write operations are performed in synchronous mode Bit 18 16 CRPGS 0x0 rw CRAM page size Cellular RAM 1 5 does not allow synchronous access to cross the address boundaries between pages When these bits are configured in synchronous mode the XMC will automatically split the access w...

Page 534: ...or flash access is enabled Bit 5 4 EXTMDBW 0x1 rw External memory data bus width This field defines the external memory data bus width 00 8 bits 01 16 bits 10 Reserved 11 Reserved Bit 3 2 DEV 0x2 rw Memory device type 00 SRAM ROM 01 PSRAM Cellular RAM or CRAM 10 NOR Flash 11 Reserved Bit 1 ADMUXEN 0x1 rw Address data multiplexing enable 0 Address data not multiplexed 1 Address data multiplexed Bit...

Page 535: ...able This bit defines whether the XMC will split a wrapped AHB access into two accesses 0 Direct wrapped access is not allowed 1 Direct wrapped access is allowed Bit 9 NWPOL 0x0 rw NWAIT polarity This bit defines the polarity of the NWAIT signal in synchronous mode 0 NWAIT active low 1 NWAIT active high Bit 8 SYNCBEN 0x0 rw Synchronous burst enable This bit allows synchronous access to Flash memor...

Page 536: ...latency is inserted on the data bus after one read operation in multiplexed or synchronous mode 0000 1 HCLK cycle is inserted 0001 2 HCLK cycles are inserted 1111 16 HCLK cycles are inserted Bit 15 8 DTST 0xFF rw Data setup time 0000 0 HCLK cycle is inserted 0001 1 additional HCLK cycle is inserted 1111 15 additional HCLK cycles are inserted Bit 7 4 ADDRHT 0xF rw Address hold time 0000 0 HCLK cycl...

Page 537: ...R 0x08 rw Bus turnaround phase for consecutive read duration This field is used to define the bus turnaround phase duration for consecutive read operations A delay is inserted between two consecutive read operations in order to avoid bus conflicts 00000000 1 HCLK cycle is inserted for consecutive read operations 00000001 2 HCLK cycles are inserted for consecutive read operations 00001000 9 HCLK cy...

Page 538: ...disabled 1 ECC enabled Bit 5 4 EXTMDBW 0x1 rw External memory data bus width This field specifies the external NAND Flash width 00 8 bits 01 16 bits 10 Reserved 11 Reserved Bit 3 DEV 0x1 rw Memory device type 0 Reserved 1 NAND Flash Bit 2 EN 0x0 rw Memory bank enable 0 Memory bank disabled 1 Memory bank enabled Bit 1 NWEN 0x0 rw Wait feature enable This bit is used to enable NAND Flash wait functi...

Page 539: ... cycle is inserted 11111111 255 additional HCLK cycles are inserted Bit 23 16 RGHT 0xFC rw Regular memory hold time This field defines the databus hold time when access to NAND Flash in a regular memory 00000000 Reserved 00000001 1 HCLK cycle is inserted 11111111 255 HCLK cycles are inserted Bit 15 8 RGWT 0xFC rw Regular memory wait time Specifies the regular memory wait time when the XMC_NWE and ...

Page 540: ...rd controller registers 24 7 3 1PC card control register XMC_BK4CTRL Accessed by words Bit Register Reset value Type Description Bit 31 3 Reserved 0x000 resd Kept at its default value Bit 2 EN 0x0 rw Memory bank enable 0 Memory bank disabled 1 Memory bank enabled Bit 1 NWEN 0x0 rw Wait feature enable This bit is used to enable PC card memory bank wait feature 0 Wait feature disabled 1 Wait feature...

Page 541: ... in a common space 00000000 Reserved 00000001 1 HCLK cycle is inserted 11111111 255 HCLK cycles are inserted Bit 15 8 CMWT 0xFC rw Common memory wait time Specifies the common memory wait time when the XMC_NWE and XMC_NOE is low 00000000 0 HCLK cycle is inserted 00000001 1 additional HCLK cycle is inserted 11111111 255 additional HCLK cycles are inserted Bit 7 0 CMST 0xFC rw Common memory setup ti...

Page 542: ...is field defines the databus hold time when access to NAND Flash in an IO space 00000000 Reserved 00000001 1 HCLK cycle is inserted 11111111 255 HCLK cycles are inserted Bit 15 8 ATWT 0xFC rw Attribute memory wait time Specifies the IO wait time when the XMC_NWE and XMC_NOE is low 00000000 0 HCLK cycle is inserted 00000001 1 additional HCLK cycle is inserted 11111111 255 additional HCLK cycles are...

Page 543: ...ne the number of internal banks 0 2 internal BANKs 1 4 internal BANKs Bit 5 4 DB 0x0 rw SDRAM data bus This field enables 8 bit or 16 bit data bus width 00 8 bits 01 16 bits 10 Reserved do not use 11 Reserved do not use Bit 3 2 RA 0x0 rw Row address This field defines the number of a row address including 11 bits 12 bits and 13 bits 00 11 bits 01 12 bits 10 13 bits 11 Reserved do not use Bit 1 0 C...

Page 544: ...les Bit 11 8 TRAS 0xF rw Self refresh time This field defines the minimum self refresh period in umber of clock cycles 0000 1 cycle 0001 2 cycles 1111 16 cycles Bit 7 4 TXSR 0xF rw Exit Self refresh to active delay This field defines the delay from exiting the self refresh command to issuing an activate command in number of clock cycles 0000 1 cycle 0001 2 cycles 1111 16 cycles Bit 3 0 TMRD 0xF rw...

Page 545: ...ved 24 7 4 4SDRAM refresh timer register SDRAM_RCNT This register is used to set the refresh rate of the SDRAM in number of SDRAM CLK clock cycles The RC has to be configured as a non zero value in order to perform a correct refresh operation The RC value cannot be changed after initialization Refresh operation has priority over a read write operation However if a read write operation is in progre...

Page 546: ... at its default value Bit 5 BUSY 0x0 ro Busy This bit indicates the status of the current SDRAM controller 0 Idle 1 Busy Bit 4 3 BK2STS 0x0 ro Bank2 status This field defines the status mode of the SDRAM Bank 2 00 Normal mode 01 Auto refresh mode 10 Power down mode Bit 2 1 BK1STS 0x0 ro Bank 1 Status This field defines the status mode of the SDRAM Bank 1 00 Normal mode 01 Auto refresh mode 10 Powe...

Page 547: ...de Interrupt requests Note The SDIO is not compatible with SPI communication mode It supports only one SD SDIO MMC 4 2 card at any one time Communication on the bus is based on command and data transfers Command A command is a token that starts an operation Commands are sent from the host either to a single card addressed command or to all connected cards broadcast command Commands are transferred...

Page 548: ...MD Response Data block crc Data from card to host Data block crc Data block crc Stop command stops data transfer Multiple block read operation Command Figure 25 3 SDIO multiple block write operation Command Response From host to card From card to host Data stop operation Block write operation SDIO_D SDIO_CMD Response Busy Busy Data from host to card Data blcok crc Data block crc Stop command stops...

Page 549: ...addressed point to point command Broadcast command applicable to all cards some need responses Addressed command sent to the addressed card and responses received from the card Memory card defines two types of operational modes Card identification mode Data transfer mode 25 3 1 1Card identification mode In card identification mode the host resets all cards validates the operation voltage range ide...

Page 550: ...transfer read write can be done in data block mode or stream mode configured by the TFRMODE bit in the SDIO_DTCTRL register In the data stream mode data is transferred in bytes and without CRC appended to the end of each data block Wide bus selection deselection Wide bus 4 bit bus width operation mode is selected or deselected by using ACMD6 SET_BUS_WIDTH The default bus width after power up or CM...

Page 551: ... at any time and the card will respond with its status The READY_FOR_DATA status bit indicates whether the car can accept new data or whether the write process in still in progress The host can deselect the card by issuing CMD7 select another card which will place the card in the disconnect state and release the SDIO_D line without interrupting the write operation When reselecting the card it will...

Page 552: ...s the card lock unlock command The lock unlock command structure is shown below Table 25 1 Lock unlock command structure Byte Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 Reserved set to 0 ERASE LOCK_UNLOCK CLR_PWD SET_PWD 1 PWDS_LEN 2 password data PWDS_LEN 1 ERASE Setting it will force an erase operation All other bits must be zero and only the command byte is sent LOCK_UNLOCK Setting it will lock ...

Page 553: ...selected previously 2 Define the block length with CMD16 SET_BLOCKLEN to send in the 8 bit card lock unlock mode 8 bit PWD_LEN and the number of bytes of the new password 3 Send CMD42 LOCK UNLOCK with the appropriate data block size on the data line including the 16 bit CRC The data block indicates the operation mode SET_PWD 1 the length PWD_LEN and the password PWD 4 When a password is matched th...

Page 554: ...and with response sent to all cards responses received from all cards simultaneously 3 Addressed command sent to the selected card and no data transfer on the SDIO_D line 4 Addressed data transfer command sent to the selected card and data transfer is present on the SDIO_D line Command description The SDIO host module system is designed to provide a standard interface for a variety of application ...

Page 555: ...n EXT_CSD register as a data block CMD9 ac 31 16 RCA 15 0 stuff bits R2 SEND_CSD The selected card sends CSD card specific data through the CMD bus CMD10 ac 31 16 RCA 15 0 stuff bits R2 SEND_CID The selected card sends CID card flag through the CMD bus CMD12 ac 31 0 stuff bits R1b STOP_TRANSMI SSION Force the card to stop transmission CMD13 ac 31 16 RCA 15 0 stuff bits R1 SEND_ STATUS Selected car...

Page 556: ...ite that follows CMD24 adtc 31 0 data address R1 WRITE_ BLOCK Write a data block of the size set by the CMD16 CMD25 adtc 31 0 data address R1 WRITE_ MULTIPLE BLOCK Continuously write data blocks until the STOP_TRANSMISSION is received CMD26 adtc 31 0 stuff bits R1 PROGRAM_ CID Program the card identification register CMD27 adtc 31 0 stuff bits R1 PROGRAM_ CSD Program the programmable bits of the C...

Page 557: ...a card CMD38 ac 31 0 stuff bits R1b ERASE Erase all previously selected data blocks Table 25 8 I O mode commands CMD index Type Parameter Response format Abbreviation Description CMD39 ac 31 16 RCA 15 register write flag 14 8 register address 7 0 register data R4 FAST_IO Used to write and read 8 bit register data fields The command specifies a card and a register and provides the data for writing ...

Page 558: ... response type are protected by a CRC Every command code word is terminated with the end bit always 1 25 3 2 2 1 R1 normal response command Code length 48 bits The 45 40 bits indicate the index of the command to be responded to This value is interpreted as a binary coded number between 0 and 63 The status of the card is coded in 32 bits Note that if it involves a data transfer to a card a busy sig...

Page 559: ... R4 response Bit 47 46 45 40 39 8 7 1 0 Field width 1 1 6 16 8 8 7 1 Value 1 0 100111 1 Description Start bit Transmiss ion bit CMD39 RCA Register address Read register contents CRC7 End bit 25 3 2 2 6 R4b For SD I O only an SDIO card will respond with a unique SDIO response R4 after receiving the CMD5 Table 25 15 R4b response Bit 47 46 45 40 39 8 7 1 0 Field width 1 1 6 1 3 1 3 24 7 1 Value 1 0 1...

Page 560: ...an I O only card In this case the 16 bits of response are the SD I O only values Bit 15 COM_CRC_ERROR Bit 14 ILLEGAL_COMMAND Bit 13 ERROR Bit 12 0 Reserved 25 3 3 SDIO functional description SDIO consists of four parts SDIO adapter block contains a control unit command path and data path that provides all functions specific to the MMC SD SD I O card such as the clock generation command and data tr...

Page 561: ...I O card and MMC V4 2 also use push pull drivers for initialization SDIO_D 7 0 is a bidirectional data channel After initialization the host can change the width of the data bus After reset the SDIO_D0 is used for data transfer by default MMCV3 31 or previous supports only one bit of data line so only SDIO_DO can be used The table below is used for the MultiMedia card SD SD I O card bus Table 25 1...

Page 562: ...rred with each SDIO_CK including start bit transfer bit command index defined by the SDIO_CMDCTRL_CMDIDX bit parameters defined by the SDIO_ARG 7 bit CRC and end bit Then receives responses from the card There are two response types 48 bit short response and 136 bit long response Both use CRC error check The received responses are saved in the area from SDIO_RSP1 to SDIO_RSP4 The command path can ...

Page 563: ...imum delay between two host commands and NRC the minimum delay between the host command and the card response When the wait state is entered the command timer is enabled If the NCR timeout response time to a command that is 64 SDIO_CK periods is reached before the CCSM moves to the receive state the timeout flag is set CMDTIMEOUT and the idle state is entered If the interrupt bit is set in the com...

Page 564: ...on the TFRDIR bit the DCSM enters Wait_S or Wait_R state Data channel state machine DCSM The DCSM has seven states in send and receive mode as shown in the Figure below Figure 25 9 Data channel state machine DCSM Idle Busy Read Wait Send Wait_R Receive After reset Wait_S Data ready Enabled and send Disabled or end of data End of packet Disabled or CRC fails or timeout Not busy Disabled or BUF unde...

Page 565: ...d it will write the data to the BUF The write pointer is incremented automatically after the end of the write operation On the other side a read pointer always points to the current data in the BUF If the receive BUF is disabled all status flags are cleared and the read and write pointers are reset as well The data path sets the DORX when it receives data 25 3 3 3SDIO AHB interface The AHB interfa...

Page 566: ...IO adapter will enter read wait state and drive the SDIO_D2 to 0 after 2 SDIO_CK cycles The data unit starts waiting to receive data from a card The DCSM will not enter read wait even if read wait start is set The read wait process will start after the CRC is received The RDWTSTOP has to be cleared to start a new read wait operation During the read wait period the SDIO host can detect the SDIO int...

Page 567: ...gister name Offset Reset value SDIO_PWRCTRL 0x00 0x0000 0000 SDIO_CLKCTRL 0x04 0x0000 0000 SDIO_ARG 0x08 0x0000 0000 SDIO_CMD 0x0C 0x0000 0000 SDIO_RSPCMD 0x10 0x0000 0000 SDIO_RSP1 0x14 0x0000 0000 SDIO_RSP2 0x18 0x0000 0000 SDIO_RSP3 0x1C 0x0000 0000 SDIO_RSP4 0x20 0x0000 0000 SDIO_DTTMR 0x24 0x0000 0000 SDIO_DTLEN 0x28 0x0000 0000 SDIO_DTCTRL 0x2C 0x0000 0000 SDIO_DTCNTR 0x30 0x0000 0000 SDIO_S...

Page 568: ...SEN 0x0 rw Clock divider bypass enable bit This bit is set or cleared by software When disabled the SDIO_CK output signal is driven by the SDIOCLK that is divided according to the CLKDIV value When enabled the SDIO_CK output signal is directly driven by the SDIOCLK 0 Clock divider bypass disabled 1 Clock divider bypass enabled Bit 9 PWRSVEN 0x0 rw Power saving mode enable This bit is set or cleare...

Page 569: ...it This bit is set or cleared by software 0 Command channel state machine disabled 1 Command channel state machine enabled Bit 9 PNDWT 0x0 rw CCSM Waits for ends of data transfer CmdPend internal signal This bit is set or cleared by software If this bit is set the CCSM waits for the end of data transfer before it starts sending a command 0 Disabled 1 Enabled Bit 8 INTWT 0x0 rw CCSM waits for inter...

Page 570: ...nificant bit of the card status is always received first The least significant bit of the SDIO_RSP4 register is always 0 25 4 7 SDIO data timer register SDIO_DTTMR The SDIO_DTTMR register contains the data timeout period in the unit of card bus clock periods A counter loads the value from the SDIO_DTTMR register and starts decrementing when the DCSM enters the Wait_R or busy state If the counter r...

Page 571: ...it starts when this bit is cleared no actions occurs 0 Read wait disabled 1 Read wait enabled Bit 7 4 BLKSIZE 0x0 rw Data block size This bit is set or cleared by software This field defines the length of data block when the block data transfer is selected 0000 block length 20 1 byte 0001 block length 21 2 bytes 0010 block length 22 4 bytes 0011 block length 23 8 bytes 0100 block length 24 16 byte...

Page 572: ...bits 23 22 10 0 These bits can be cleared by writing to the SDIO_INTCLR register Dynamic flags bit 21 11 These bit status changes with the state of the corresponding logic for example BUT full or empty flag is set or cleared as data written to the BUF Bit Register Reset value Type Description Bit 31 23 Reserved 0x000 resd Kept at its default value Bit 22 IOIF 0x0 ro SD I O interrupt received Bit 2...

Page 573: ...SPCMPL flag Bit 5 RXERRO 0x0 rw RXERRO flag clear bit This bit is set by software to clear the RXERRO flag Bit 4 TXERRU 0x0 rw TXERRU flag clear bit This bit is set by software to clear the TXERRU flag Bit 3 DTTIMEOUT 0x0 rw DTTIMEOUT flag clear bit This bit is set by software to clear the DTTIMEOUT flag Bit 2 CMDTIMEOUT 0x0 rw CMDTIMEOUT flag clear bit This bit is set by software to clear the CMD...

Page 574: ...nable This bit is set or cleared by software to enable disable the Data receive acting interrupt 0 Disabled 1 Enabled Bit 12 DOTXIEN 0x0 rw Data transmit acting interrupt enable This bit is set or cleared by software to enable disable the Data transmit acting interrupt 0 Disabled 1 Enabled Bit 11 DOCMDIEN 0x0 rw Command acting interrupt enable This bit is set or cleared by software to enable disab...

Page 575: ... the Data CRC fail interrupt 0 Disabled 1 Enabled Bit 0 CMDFAILIEN 0x0 rw Command CRC fail interrupt enable This bit is set or cleared by software to enable disable the Command CRC fail interrupt 0 Disabled 1 Enabled 25 4 14SDIOBUF counter register SDIO_BUFCNTR The SDIO_BUFCNTR register contains the number of words to be written to or read from the BUF The BUF counter loads the value from the SDIO...

Page 576: ...he transmission and reception of the frame is scheduled by DMA DMA features Programmable AHB burst transfer types Supports ring or chained descriptor Each descriptor can transfer up to 8 KB of data Poll or fixed priority arbitration between transmission and reception Programmable interrupts for different operational conditions Status information report for each transfer EMAC core features Supports...

Page 577: ... and a dedicated DMA controller It implements the following functions Data transmit and receive Framing frame boundary and frame synchronization Handling of source and destination addresses Error detection Media access management in half duplex mode Medium allocation avoid collision Collision resolve handle collision Usually there are two operating modes for the MAC sublayer Half duplex mode The s...

Page 578: ...It is cleared by the SMI interface at the end of read operation Attention should be paid to the fact that the contents of the EMAC_MACMIIADDR and EMAC_MACMIIDT registers are not allowed to change The application should not change these register contents After the transaction the EMAC_MACMIIDT register is automatically updated with the data read from the SMI The SMI clock source is a divided AHB cl...

Page 579: ...lled by the PHY and can be valid only in half duplex mode This signal is enabled upon detection of a collision on the medium and will remain enabled during the duration of the collision This signal is not required to be synchronized with the TX and RX clocks MII_RXD 3 0 It is controlled by the PHY Four bit data to be received are transmitted synchronously Data is valid when the MII_RX_DV signal is...

Page 580: ... requires 16 pins for data and control signals while the RMII reduces the pin count to 7 pins a 62 5 decrease in pin count The RMII interface is used to connect the EMAC and the PHY This helps translate the MAC MII signal to the RMII Figure 26 4 Reduced media independent interface signals EMAC RMII SMI MDC MDIO CRS_DV RXD 1 0 TX_EN TXD 1 0 REF_CLK CLOCK PHY MII RMII selection and clock sources Eit...

Page 581: ...re 26 6 MII clock sources provided by an external oscillator AT32F407 EMAC TX_CLK RX_CLK PHY 25MHZ OSC RMII clock sources As shown in Figure 26 7 both the EMAC and PHY require 50MHz clock sources which can be done with an external crystal oscillator or CLKOUT pin When the CLKOUT pin is used the PLL has to be configured to generate this clock Refer to CRM section for more information ...

Page 582: ...reset state EMAC_MII_RX_DV EMAC_RMII_CRS_DV RX_DV CRS_DV PA7 Floating input reset state EMAC_MII_RXD0 EMAC_RMII_RXD0 RXD0 RXD0 PC4 Floating input reset state EMAC_MII_RXD1 EMAC_RMII_RXD1 RXD1 RXD1 PC5 Floating input reset state EMAC_MII_RXD2 RXD2 PB0 Floating input reset state EMAC_MII_RXD3 RXD3 PB1 Floating input reset state EMAC_MII_RX_ER RX_ER PB10 Floating input reset state EMAC_MII_TX_EN EMAC...

Page 583: ... using the MAC address and multicast HASH table The address filtering status is reported accordingly Unicast destination address filter There are two filtering modes perfect address filtering and HASH table filtering 1 Perfect address filtering It is enabled by setting HUC 0 in the frame filtering register Four MAC addresses are used for perfect filtering The MACADDR0 is always enabled The MACADDR...

Page 584: ...it HASH table is used to perform imperfect filtering Broadcast address filter If the DBF is set in the frame filter register the EMAC will reject all broadcast frames If DBF 0 the EMAC will accept all broadcast frames Unicast source address filter If the bit 30 is set in the MAC address register 1 2 3 the filter will compare source address instead of destination address of the received frames If t...

Page 585: ...rames if PCF 0x Table 26 6 Source address filtering Frame type PR SAIF SAF SA filter operation Unicast 1 X X Pass all frames 0 0 0 Pass status on perfect group filter match but do not drop frames that failed 0 1 0 Fail status on perfect group filter match but do not drop frames that failed 0 0 1 Pass on perfect group filter match and drop frames that failed 0 1 1 Fail on perfect group filter match...

Page 586: ...collision occurs at any time from the beginning of a frame to the end of the CRC the collision signal is sent to the EMAC core The EMAC core will send a 32 bit jam signal of 0x5555 5555 to inform all other stations on the LAN that a collision has occurred If the collision happened during the preamble transmission phrase the EMAC completes the transmission of the preamble and SFD and then sends the...

Page 587: ...pplication DMA All data that do not start with an SOF marker will be discarded after the flush operation Transmit status word and time stamp At the EMAC controller has completed the transmission of the Ethernet frame the transmit status is given to the application If IEEE 1588 time stamp is enabled a 64 bit time stamp along with the transmit status will be written to the transmit descriptor Transm...

Page 588: ... no error is reported When the first type of error is detected the TCP UDP or ICMP header is not modified For the second type of error the calculated checksum is still inserted into the corresponding header field EMAC frame reception The MAC received frames are stored into the RXFIFO and sent out by the DMA using the AHB interface There are two modes Cut through mode and store and forward mode In ...

Page 589: ...data length does not match that of the IP headers 2 The calculated checksum does not equal the value of the TCP UDP or ICMP checksum field Receive flow control In Full duplex mode the MAC detects the receiving Pause frame and pauses the frame transmission according to the delay specified within the received Pause frame The ERF bit in the EMAC_MACFCTRL register to enable or disable Pause frame dete...

Page 590: ...r SRAM via the AHB master interface DMA control and status register and descriptor table are used to manage the whole transmission and reception process which has its respective descriptor list The descriptor list is usually stored in the system buffer area SRAM When the transmission and reception is enabled the DMA polls the descriptor table through the transmit and receive poll register to start...

Page 591: ...r size calculation For transmission software needs to calculate the buffer size The TXDMA transfers the exact number of bytes programmed by buffer size field in the TDES1 to the EMAC core If the FS bit is set in the TDES0 the DMA marks the first transfer from the buffer as the start of frame If the LS bit is set in the TDES0 the DMA marks the last transfer from the buffer as the end of frame Durin...

Page 592: ... are repeated until the end of frame data is transferred 6 When the frame transmission is complete if IEEE1588 time stamping was enabled for the frame as indicated in the transmit status the time stamp value is written to the transmit descriptor TDES2 and TDES3 that contains the end of frame buffer while the transmit status information is sent to the TDES0 Then the OWN bit is cleared and the curre...

Page 593: ...ted the DMA writes back the final status information to the TDES0 If the transmit complete interrupt bit TDES0 30 is set the transmit interrupt bit EMAC_DMASTS bit 0 is set the next descriptor is fetched and the above steps are repeated Actual frame transmission depends on whether the store and forward mode or threshold mode is selected The descriptor is disabled TDES0 31 is cleared when the DMA f...

Page 594: ... calculation and insertion are enabled but pseudo header checksum is not calculated 11 IP header checksum and data checksum calculation and insertion are enabled and pseudo header checksum is calculated Bit 21 TER rw Transmit end of ring When set it indicates that the descriptor list reached its final descriptor The DMA returns to the start address of the list creating a descriptor ring Bit 20 TCH...

Page 595: ...ry disabled bit in the EMAC_MACCTRL register is set then this bit is set after the first collision and the transmission of the frame is aborted Bit 7 VF rw VLAN frame When set this bit indicates that the transmitted frame is a VLAN type frame Bit 6 3 CC rw Collision count This field indicates the number of collisions experienced before the frame was transmitted This bit is invalid when the EC bit ...

Page 596: ...a descriptor chain structure is used these bits indicate the physical address of the next descriptor TTSH Transmit frame time stamp high The DMA updates these bits with the 32 most significant bits of the time stamp captured for the corresponding frame This field has the time stamp only when the TTSE bit in the TDES0 and the LS bit for the frame are set RXDMA configuration 1 The application sets u...

Page 597: ... of the frame in the buffer The descriptors are released by clearing the OWN bit when the data buffer fills up or at the end of the frame reception If the current descriptor buffer is enough to accommodate the complete frame the current description RDES0 LS and FS bits are set The DMA fetches the next descriptor sets the LS bit in the previous descriptor writes the receive status word to the previ...

Page 598: ...he bit 7 and bit 25 in the EMAC_MACCTRL register Bit 15 ES rw Error summary This bit indicates the logical OR of the following bits RDES0 1 CRC error RDES0 3 Receive error RDES0 4 Watchdog timeout RDES0 6 Late collision RDES0 7 Giant frame or IP checksum error RDES0 11 Overflow error RDES0 14 Descriptor error Bit 14 DE rw Descriptor error When set this bit indicates a frame truncation caused by a ...

Page 599: ...d while the RX_DV is valid during frame reception Bit 2 DE rw Dribble bit error When set this bit indicates that the received frame is not an integer multiple of bytes odd nibbles This bit is valid only in MII mode Bit 1 CE rw CRC error When set this bit indicates a CRC error occurred on the received frame This bit is valid only when the LS bit is set Bit 0 PCE rw Payload checksum error When set t...

Page 600: ... Name Type Description Bit 31 0 RBAP1 R TSL rw Receive buffer 1 address pointer Receive frame time stamp low These bits have two functions The application uses them to indicate to the DMA where to store the data in memory After completing data reception the DMA may use these bits to store frame time stamp RBAP1 When this descriptor is owned by the DMA these bits indicate the physical address of bu...

Page 601: ...16 Filter I byte mask This register defines which bytes of the filter i i 0 3 are used to determine whether or not the frame is a wakeup frame The bit 31 must be zero The bit j 30 0 is the byte mask If the bit j is set then filter i offset j of the incoming frame will be processed by the CRC block otherwise filter i offset j is ignored Filter i command This is a 4 bit command Bit 3 defines the add...

Page 602: ... is still able to detect frames as long as the EXTI 19 is enabled However the RE bit has to be set in the EMAC_MACCTRL register because the EMAC needs to detect Magic Packet or a remote wakeup frame DEEPSLEEP and wakeup sequences are recommended as follows 1 Disable the TXDMA and wait for all data transmission to complete These transmissions can be checked by polling the TI bit in the EMAC_DMASTS ...

Page 603: ...AC will capture the time stamp of all the received frames on the MII The upper 32 bits and the lower 32 bits of the time stamp are stored in the RDES3 and RDES2 respectively so that the time stamp and receive status work will be returned to the application all together System time correction methods The PTP input reference clock is the system clock SYSCLK which is used to update the 64 bit time st...

Page 604: ...o If the MasterToSlaveDelay is assumed to be the same for consecutive Sync messages The algorithm below mentioned must be applied After a few Sync cycles the frequency is locked The slave clock can then determine an accurate MasterToSlaveDela value and synchronize the master with the salve clock using the new value The algorithm is shown as follows When the master clock is MasterSyncTimen the mast...

Page 605: ...or negative to the Ethernet PTP time stamp high update register EMAC_PTPTSHUD and the Ethernet PTP time stamp low update register EMAC_PTPTSLUD 2 Set the bit 3 TU in the Ethernet PTP time stamp control register EMAC_PTPTSCTRL 3 When the TU bit is cleared the value in the time stamp update registers is added to or subtracted from the system time Programming steps for system time update using fine c...

Page 606: ... duty cycle of the PPS output is 50 when the binary rollover control is selected Set the bit 30 in the IOMUX_REMAP register to enable PPS output feature Figure 26 17 PPS output EMAC PPS OUTPUT 26 2 6 EMAC interrupts The EMAC has two interrupt vectors one is used for normal Ethernet operations and the other for the Ethernet wakeup event remote wakeup frame or Magic Packet detection when it is mappe...

Page 607: ...t values The peripheral registers can be accessed by bytes 8 bit half words 16 bit or words 32 bit Table 26 8 Ethernet register map and its reset values Register name Offset Reset value EMAC_MACCTRL 0x00 0x0000 8000 EMAC_MACFRMF 0x04 0x0000 0000 EMAC_MACHTH 0x08 0x0000 0000 EMAC_MACHTL 0x0C 0x0000 0000 EMAC_MACMIIADDR 0x10 0x0000 0000 EMAC_MACMIIDT 0x14 0x0000 0000 EMAC_MACFCTRL 0x18 0x0000 0000 E...

Page 608: ...00 0000 EMAC_MMCRFCECNT 0x194 0x0000 0000 EMAC_MMCRFAECNT 0x198 0x0000 0000 EMAC_MMCRGUFCNT 0x1C4 0x0000 0000 EMAC_PTPTSCTRL 0x700 0x0000 2000 EMAC_PTPSSINC 0x704 0x0000 0000 EMAC_PTPTSH 0x708 0x0000 0000 EMAC_PTPTSL 0x70C 0x0000 0000 EMAC_PTPTSH 0x708 0x0000 0000 EMAC_PTPTSL 0x70C 0x0000 0000 EMAC_PTPTSHUD 0x710 0x0000 0000 EMAC_PTPTSLUD 0x714 0x0000 0000 EMAC_PTPTSAD 0x718 0x0000 0000 EMAC_PTPTT...

Page 609: ...me Gap These bits are used to define the minimum interframe gap between frames during transmission 000 96 bit times 96 bit times 001 88 bit times 88 bit times 010 80 bit times 80 bit times 111 40 bit times 40 bit times In half duplex mode the minimum IFG can be configured as 64 bit times IFG 100 Lower values are not allowed Bit 16 DCS 0x0 rw Disable Carrier Sense When this bit is set the MAC trans...

Page 610: ...l ignore the current frame transmission and report a frame abort because of excessive collision error in the transmit frame status When this bit is cleared the MAC attempts retries based on the settings of BL 6 5 This bit is applicable only in half duplex mode It is reserved with default value RO in For full duplex mode only mode Bit 8 Reserved 0x0 resd Kept at its default value Bit 7 ACS 0x0 rw A...

Page 611: ...ween two consecutive operations Bit 1 0 Reserved 0x0 resd Kept at its default value 26 3 2 Ethernet MAC frame filter register EMAC_ MACFRMF The Ethernet MAC frame filter register contains the filter control bits for receiving frames Some of the control bits got to the address check block of the MAC to perform the first level of address filtering The second level of filtering is performed on the in...

Page 612: ...adcast Frames When this bit is set the address filters filter all incoming broadcast frames In addition all other filter settings will also be overwritten When this bit is set the address filters pass all incoming broadcast frames Bit 4 PMC 0x0 rw Pass MultiCast When this bit is set all frames with a multicast destination address first bit in the destination address is set are passed When this bit...

Page 613: ...iltering Bit Register Reset value Type Description Bit 31 HTH 0x0000 0000 rw This bit contains the upper 32 bits of the Hash table 26 3 4 Ethernet MAC Hash table low register EMAC_MACHTL The EMAC_MACHTL register contains the lower 32 bits of the Hash table If the Hash filter is disabled or either 128 bit or 256 bit Hash table is selected both register 2 and register 3 are reserved Bit Register Res...

Page 614: ...erved 0x0000 resd Kept at its default value Bit 15 0 MD 0x0000 rw MII Data This field contains the 16 bit value from the PHY after a read operation or the 16 bit value to be written to the PHY before a write operation 26 3 7 Ethernet MAC flow control register EMAC_MACFCTRL The Ethernet MAC flow control register controls the generation and reception of the control frames by the MAC flow control blo...

Page 615: ... the received Pause frame and disables the transmitter for a period of time When this bit is cleared the decode function of the Pause frame is disabled Bit 1 ETF 0x0 rw Enable Transmit Flow control In full duplex mode when this bit is set the MAC enables the flow control operation to transmit Pause frames When this bit is cleared the flow control of the MAC is disabled and the MAC does not transmi...

Page 616: ...leared the 16 bits of the received VLAN frame s 15th and 16th bytes are used for comparison and VLAN hash filtering Bit 15 0 VTI 0x0000 rw VLAN Tag Identifier for receive frames This field contains the 802 1Q VLAN tag to identify VLAN frames which is compared with the 15th and 16th bytes of the received VLAN frames described as follows Bit 15 13 User priority Bit 12 Canonical format indicator CFI ...

Page 617: ...eup frame reception Bit 1 EMP 0x0 rw Enable Magic Packet When this bit is set it indicates that the power management event is generated due to a Magic packet reception Bit 0 PD 0x0 rw1s Power Down When this bit is set the MAC receiver will drop all received frames after receiving the expected Magic packet or a remote wakeup frame Then this bit is automatically cleared and power down mode is disabl...

Page 618: ... PIM 0x0 rw PMT Interrupt Mask When this bit is set it masks the interrupt signal generated in the MPT interrupt status bit of the EMAC_MACISTS register Bit 2 0 Reserved 0x0 resd Kept at its default value 26 3 13Ethernet MAC address 0 high register EMAC_MACA0H The EMAC_MACA0H register contains the upper 6 bits of the first 6 byte MAC address of the station The first DA byte received on the MII int...

Page 619: ... is cleared the address filter will ignore the address for filtering Bit 30 SA 0x0 rw Source Address When this bit is set the MAC address 1 47 0 is used for comparison with the source address field of the received frame When this bit is cleared the MAC address 1 47 0 is used for comparison with the destination address field of the received frame Bit 29 24 MBC 0x00 rw Mask Byte Control These bits a...

Page 620: ...er Each control bit is used for controlling the mask of the bytes as follows Bit 29 EMAC_MACA2H 15 8 Bit 28 EMAC_MACA2H 7 0 Bit 27 EMAC_MACA2L 31 24 Bit 24 EMAC_MACA2L 7 0 It is possible to filter group addresses that is group address filtering by masking one or more bytes of the address Bit 23 16 Reserved 0x00 resd Kept at its default value Bit 15 0 MA2H 0xFFFF rw MAC Address2 High 47 32 These bi...

Page 621: ...6 byte second MAC address Bit Register Reset value Type Description Bit 31 0 MA3L 0xFFFF FFFF rw MAC Address3 Low 31 0 These bits contain the lower 32 bits of the 6 byte second MAC address The contents of this field is undefined until loaded by the application after the initialization process 26 3 21Ethernet DMA bus mode register EMAC_DMABM The Ethernet DMA bus mode register defines the bus operat...

Page 622: ...A always attempts to perform burst transfer as specified in PBL each time it starts a burst transfer on the host bus The RPBL can be programmed with 1 2 4 8 16 and 32 Any other value result in unexpected behavior When the USP is set the PBL value is applicable to Tx DMA operations only If the number of beats to be transferred is greater than 32 the following steps are required 1 Set PBLx8 mode 2 S...

Page 623: ...enter suspend mode due to the unavailability of descriptors owned by it Bit Register Reset value Type Description Bit 31 0 RPD 0x0000 0000 rrc Receive Poll Demand When these bits are written with any value the DMA reads the current descriptor pointed to by the EMAC_DMACRD If the descriptor is not available owned by host the reception suspends and the bit 7 RU is set in the status register If the d...

Page 624: ...ster clears them Writing 1 b0 has no effect Each bit bit 16 0 can be masked through the corresponding bit in the interrupt enable mask register Bit Register Reset value Type Description Bit 31 30 Reserved 0x0 resd Kept at its default value Bit 29 TTI 0x0 ro Timestamp Trigger Interrupt This bit indicates an interrupt event in the time stamp generator block The software must read the corresponding r...

Page 625: ...eive interrupt EMAC_DMASTS 14 Early receive interrupt Only unmasked bits affect the normal interrupt summary This is a sticky bit and it must be cleared by writing 1 to this bit each time a corresponding bit causes NIS to be set is cleared Bit 15 AIS 0x0 rw1c Abnormal Interrupt Summary The abnormal interrupt summary value is the logic OR of the following bits when the corresponding interrupt bits ...

Page 626: ...derflow error bit TDES0 1 is set Bit 4 OVF 0x0 rw1c Receive Overflow This bit indicates that the receive buffer has an overflow during a frame reception If the partial frame has been transferred to the application the overflow status is set in the RDES0 11 Bit 3 TJT 0x0 rw1c Transmit Jabber Timeout This bit indicates that the transmit Jabber timer will expire when the current frame is greater than...

Page 627: ...ansmit process stops Bit 20 FTF 0x0 rw Flush Transmit FIFO When this bit is set the Tx FIFO controller logic is reset of its default values and thus all data in the Tx FIFO are either lost or flushed This bit is cleared after the completion of the flushing operation The operation mode register should not be written before this bit is cleared The data that has been received by the MAC transmitter i...

Page 628: ...d frames including pad bytes and CRC with no error and length less than 64 bytes When this bit is cleared the Rx FIFO drops all frames with a length less than 64 bytes unless such a frame has already been transferred to the application due to a lower value than the receive threshold e g RTC 01 Bit 5 Reserved 0x0 resd Kept at its default value Bit 4 3 RTC 0x0 rw Receive Threshold Control These two ...

Page 629: ...d When this bit is cleared an abnormal interrupt summary is disabled This bit enables the following bits in the status register EMAC_DMASTS 1 Transmit process stopped EMAC_DMASTS 3 Transmit Jabber timeout EMAC_DMASTS 4 Transmit overflow EMAC_DMASTS 5 Transmit data underflow EMAC_DMASTS 7 Transmit buffer u unavailable EMAC_DMASTS 8 Receive process stopped EMAC_DMASTS 9 Receive watchdog timeout EMAC...

Page 630: ...en this bit is cleared the transmit stopped interrupt is disabled Bit 0 TIE 0x0 rw Transmit Interrupt Enable When this bit is set with the normal interrupt summary enable bit the transmit interrupt is enabled When this bit is cleared the transmit interrupt is disabled The Ethernet interrupt is generated only when the TST or PMT bit is set in the DMA status register with other interrupts unmasked o...

Page 631: ...ion 26 3 32Ethernet DMA current transmit buffer address register EMAC_DMACTBADDR The EMAC_DMACTBADDR register points to the transmit buffer address being read by the DMA Bit Register Reset value Type Description Bit 31 0 HTBAP 0x0000 0000 ro Host Transmit Buffer Address Pointer These bits are cleared when reset The DMA updates the pointer during operation 26 3 33Ethernet DMA current receive buffer...

Page 632: ...the maximum value Bit 5 RFCE 0x0 rrc Received Frames CRC Error This bit is set when the receive frame with CRC error reaches the maximum value or half the maximum value Bit 4 0 Reserved 0x00 resd Kept at its default value 26 3 36Ethernet MMC transmit interrupt register EMAC_MMCTI The EMAC_MMCTI register contains the interrupts generated in the following conditions when the transmit statistic count...

Page 633: ...errupts generate when the transmit statistic counters reach half their maximum values or their maximum values This register is a 32 bit register Bit Register Reset value Type Description Bit 31 22 Reserved 0x000 resd Kept at its default value Bit 21 TGFCIM 0x0 rw Transmitted Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the transmitted good frame counter reaches half ...

Page 634: ...MCRFAECNT This register maintains the number of the received frames with alignment error Bit Register Reset value Type Description Bit 31 0 RFAEC 0x0000 0000 ro Received Frames Alignment Error Counter Received frames with alignment error 26 3 44Ethernet MMC received good unicast frames counter register EMAC_MMCRGUFCNT This register maintains the number of the received good unicast frames Bit Regis...

Page 635: ...l or Binary Rollover Control When this bit is set time stamp low register starts rolling after the 0x3B9A_C9FF value 1 ns precision and the time stamp high second is incremented When this bit is cleared the rollover value of the subsecond register is 0x7FFF_FFFF The subsecond increment must be configured according to PTP reference clock frequency and the value of this bit Bit 8 ETAF 0x0 rw Enable ...

Page 636: ...Ethernet PTP subsecond increment register EMAC_PTPSSINC This register is present only when the IEEE1588 time stamp function is selected without an external time stamp input In Coarse Update mode TSCFUPDT bit the value in this register is added to the system time every clk_ptp_ref_i clock cycle In Fine Update mode the value in this register is added to the system time whenever the accumulator has a...

Page 637: ...0000 rw Timestamp Second This field indicates the second value that is to be initialized or added to the system time 26 3 50Ethernet PTP time stamp low update register EMAC_PTPTSLUD This register is present only when the IEEE1588 time stamp function is selected without an external time stamp input Bit Register Reset value Type Description Bit 31 AST 0x0 rw Add or Subtract Time When this bit is set...

Page 638: ...thernet PTP time stamp status register EMAC_PTPTSSR Bit Register Reset value Type Description Bit 31 2 Reserved 0x0000 0000 resd Kept at its default value Bit 1 TTTR 0x0 ro Timestamp Target Time Reached When this bit is set it indicates the value programmed when the system time equals or exceeds the target time second register and target time nanosecond register Bit 0 TSO 0x0 ro Timestamp Seconds ...

Page 639: ...011 For binary rollover 8hz duty cycle 50 For digital rollover 4hz digital rollover is not recommended 1111 For binary rollover 32 768khz duty cycle 50 For digital rollover 16 384khz digital rollover is not recommended Digital rollover is not recommended when the PPS is non zero value because PPS output waveforms will be irregular although its average frequency is always correct in any one second ...

Page 640: ...eption through status and error interrupts Figure 27 1 DVP block diagram Synchronization code detector DVP_D 13 0 DVP_PCLK Data extractor DVP_HSYNC DVP_VSYNC Frame rate control unit Cropping control unit Resizing control unit Output FIFO DMA controller Image data formatter Processing control unit Control Status Register AHB I F DMA I F Interrupt 27 2Introduction 8 bit 10 bit 12 bit or 14 bit paral...

Page 641: ...f the digital video camera The vertical synchronization signals are used for interframe separation and it is activated by the DVP_VSYNC pin to enable DVP to split frames The vertical synchronization signals are expressed in two types Frame start In this mode the vertical synchronization signals are used as a frame start signal The Frame start signal indicates the end of the current frame and the s...

Page 642: ...era suppliers The embedded code synchronization provides synchronization information in two types FS FE LS LE type In this mode the CMOS camera uses four embedded synchronization codes to provide synchronization information The Frame Start FS synchronization code is embedded between blanking area and valid pixels signaling the start of a new frame The data following the FS is the valid pixel data ...

Page 643: ...rame composition Vertical blanking Vertical blanking Blanking SAV Active SAV Active EAV Horizontal blanking DataLine 0 DataLine N 1 Blanking SAV Blanking EAV Blanking EAV Horizontal blanking DataLine 1 Some of the CMOS cameras use some bits of the forth codes in one or several synchronization codes to pass on additional information The DVP_SUR register can be used to mask the comparison behavior o...

Page 644: ... 2 3 27 3 4 Single frame and continuous capture modes The digital video parallel interface DVP supports two types of capture single frame and continuous capture Single frame mode A single frame mode is selected by setting CFM 1 in the DVP_CTRL register In this mode after the CAP bit is set in the DVP_CTR register the DVP interface starts sampling data on the next frame start based on the received ...

Page 645: ...ed each time the DVP receives a 32 bit data After receiving a DMA request the DMA interface accesses the DVP_DT register once When the DMA interface uses DMA only single transfer mode is supported To use EMDA in this mode the peripheral burst transfer must be set as single transfer mode PBURST 0 Note To ensure correct data acquisition using DMA access interface the AHB bus clock AHB_CLK must be hi...

Page 646: ...control interrupt signals and it can be programmed to enable the synchronization status or error interrupts of the corresponding bits and send them to CPU The interrupts after enabled are stored in the read only DVP_ISTS register which is used to check the event sources The status in the DVP_ESTS and DVP_ISTS can be cleared by setting the corresponding bit in the DVP_ICLR register The DVP_ICLR is ...

Page 647: ...ature The frame rate control feature applies to continuous capture mode CFM 0 It consists of a basic frame rate control and progressive frame rate control Figure 27 9 Block diagram of frame rate control feature BFRC or EFRC Basic frame rate control Capture a frame per two frames or per two four frames which is programmable by the BFRC bit in the DVP_CTR register Enhanced frame rate control To acqu...

Page 648: ...ge It consists of a basic image capture drop control and advanced image resizing feature Figure 27 11 Image resizing block diagram Image Image PCDC LCDC or EISR Basic image capture drop control feature The basic image capture drop control feature is enabled through the PCDC or LCDC bit in the DVP_CTRL register After the LCDC bit is set to 1 drop one out of every two captured image lines to halve t...

Page 649: ... 437 Series Reference Manual 2022 11 11 Page 649 Rev 2 03 Figure 27 12 LCDC LCDS and frame structure 0 1 2 3 M 2 M 1 LCDC 0 0 1 2 3 M 2 M 1 LCDC 1 PCDS 0 0 1 2 3 M 2 M 1 LCDC 1 PCDS 1 Captured line Dropped line ...

Page 650: ...ure EFDM 1 must be set and the EFDF must be programmed based on the output formats of the CMOS video camera Refer to Section 27 7 3 for more information When the enhanced image reduction feature is used PCDC 0 and LCDC 0 must be configured and the EISRE bit must be set in the DVP_ACTRL register The DVP adjusts the size of the horizontal axis of an image through the HSRSF and HSRTF bits in the DVP_...

Page 651: ...ly The first pixel clock outputs the lower part of R and G components the second pixel clock outputs the upper part of G component and B component Or the first pixel clock outputs the lower part of B and G components and the second pixel clock outputs the upper part of G component and R component Figure 27 14 gives an example of DVP data capture and packing in RGB565 format Figure 27 14 RGB565 for...

Page 652: ...n 8 bit format The chroma components U and V are interleaved among pixels and two adjacent pixels use different chroma components The camera outputs a group of pixel components every pixel clock with Y component output on the first pixel clock and U or V component output on the second pixel clock Or the first pixel clock outputs U or V component and the second pixel clock outputs Y component Figur...

Page 653: ...ed as a data enable signal without line separation information Because the JPEG size is programmable the remaining data are padded with 0 at the end of the current frame in order to fill a word data 32 bit Note The crop feature and image scaling feature must not be used in the JPEG format 27 7 3 Enhanced data management Enhanced image scaling resize and monochrome image binarization are handled in...

Page 654: ...0 DVP_ISTS 0x010 0x0000 0000 DVP_ICLR 0x014 0x0000 0000 DVP_SCR 0x018 0x0000 0000 DVP_SUR 0x01C 0x0000 0000 DVP_CWST 0x020 0x0000 0000 DVP_CWSZ 0x024 0x0000 0000 DVP_DT 0x028 0x0000 0000 DVP_ACTRL 0x040 0x0000 0000 DVP_HSCF 0x048 0x0000 0000 DVP_VSCF 0x04C 0x0000 0000 DVP_FRF 0x050 0x0000 0000 DVP_BTH 0x054 0x0000 0000 27 8 1 DVP control register DVP_CTRL Bit Register Reset value Type Description ...

Page 655: ...res 14 bit data Bit 9 8 BFRC 0x0 rw Basic frame rate control 0 All frames are captured or use enhanced frame rate control feature 1 Enable frame rate control every alternate frame captured 2 Enable frame rate control one frame in 4 frames captured 3 Reserved This feature is valid only when CFM 0 is asserted Bit 7 VSP 0x0 rw DVP_VSYNC polarity This bit defines the vertical synchronization signals F...

Page 656: ...cal synchronization is in blanking state This bit is valid when the CAP is set Bit 0 HSYN 0x0 ro Horizontal synchronization status 0 Horizontal synchronization is not in blanking state 1 Horizontal synchronization is in blanking state This bit is valid when the CAP is set 27 8 3 DVP event status register DVP_ESTS Bit Register Reset value Type Description Bit 31 5 Reserved 0x0000 000 resd Kept at i...

Page 657: ...d 1 Horizontal synchronization interrupt generated It is cleared by writing 1 to the HSIC bit in the DVP_ICLR register Bit 3 VSIS 0x0 ro Vertical synchronization interrupt status 0 No vertical synchronization interrupt generated 1 Vertical synchronization interrupt generated It is cleared by writing 1 to the VSIC bit in the DVP_ICLR register Bit 2 ESEIS 0x0 ro Embedded synchronization error interr...

Page 658: ...LNEC Bit 15 8 LNSC 0x00 rw Line start synchronization 4th code The code consists of 4 consecutive data All 1 all 0 all 0 and LS4 Line start delimiter 4th data LS4 is composed of LNSC Bit 7 0 FMSC 0x00 rw Frame start synchronization 4th code In embedded synchronization mode if the FMSC and FMSU both are programmed to 0xFF the decoder performs embedded synchronization for non frame start synchroniza...

Page 659: ... Register Reset value Type Description Bit 31 30 Reserved 0x00 resd Kept at its default value Bit 29 16 CVNUM 0x00 rw Crop window vertical line number minus one This field specifies the number of lines of a crop window in vertical axis CVNM1 N indicates that N 1 data has been cropped from the vertical axis Bit 15 14 Reserved 0x00 resd Kept at its default value Bit 13 0 CHNUM 0x00 rw Crop window ho...

Page 660: ...format 2 RGB565 and RGB555 data format 3 Y8 Y only data format This configuration is valid when EFDM 1 is asserted Bit 3 PCDES 0x0 rw Basic pixel capture drop extended selection This register works with a basic pixel capture drop selection PCDS PCDS 0 0 Capture the first pixel data and drop others 1 Capture the second pixel data and drop others PCDS 1 0 Capture the third pixel data and drop others...

Page 661: ...3 Reserved 0x0 resd Kept at its default value Bit 12 0 VSRSF 0x00 rw Vertical scaling resize source factor When EISRE 1 this register must not be 0 27 8 15DVP enhanced frame rate control factor register DVP_FRF Bit Register Reset value Type Description Bit 30 13 Reserved 0x00000 resd Kept at its default value Bit 12 8 EFRCTF 0x00 rw Enhanced frame rate control target factor When EFRE 1 this regist...

Page 662: ...ck diagram 28 3QSPI command slave port 28 3 1 QSPI command slave port The ATQSPI020 has a command slave interface that contains register and data ports The users can access registers or data ports using this interface The command word register must be written sequentially CMD_W3 is the last to be written and is accessible in words while any other registers including data port register can be acces...

Page 663: ...x10 register cannot be used meaning that the bit 20 of the 0x10 register is set to 1 and the XIP port cannot be aborted with this bit which means that port switch must be performed in sequence The user s system must have a main Flash memory in which the user can load the port switch code and perform switching operation 28 3 5 XIP port prefetch The XPI port supports read prefetch with 2 channel rea...

Page 664: ...ation Figure 28 5 Status read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Instruction 05h or 35h Status Register 1 or 2 Out 3 2 1 6 5 4 7 0 CS CLK DI Mode0 Mode3 23 Status Register 1 or 2 Out 3 2 1 6 5 4 7 0 High Impendance DO MSB To execute a read data command set instruction code and length to 1 byte address address size to 3 bytes and set write instruction to 0 Refer to Figure 28...

Page 665: ...ze enable continuous read mode continuous read mode code and dual I O operation Refer to Figure 28 8 for details Figure 28 8 Quick read dual wire I O Instruction BBh CS IO0 31 32 33 34 35 36 37 38 4 2 0 6 39 CS CLK IO0 5 3 1 7 4 2 0 6 5 3 1 7 4 2 0 6 5 3 1 7 4 2 0 6 5 3 1 7 30 24 25 26 27 28 29 23 IO1 IO1 Byte 1 Byte 2 Byte 3 6 7 IO Switches from Input to Output MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13...

Page 666: ...from Input to Output Byte 1 Byte 2 Byte 3 Byte 4 To execute a quick read quad I I command set instruction code length address address size the second dummy period continuous read mode code and enable quad I O mode Refer to Figure 28 10 for more information Figure 28 10 Quick read quad I O command 0 4 0 4 1 5 1 5 0 4 0 4 1 5 1 7 2 6 2 6 2 6 2 6 3 7 3 7 3 7 3 7 A32 16 A15 8 A7 0 M7 0 0 1 2 3 4 5 6 7...

Page 667: ...it 31 29 Reserved 0x0 resd Kept at its default value Bit 28 PEMEN 0x0 rw Performance enhanced mode enable Locates between the address and the second pseudo state In this mode the command status after the second read command can be removed Do not set this bit when CMD_W2 0 0 Performance enhanced mode disabled 1 1 byte Performance enhanced mode enabled Bit 27 26 Reserved 0x0 resd Kept at its default...

Page 668: ...15 3 Reserved 0x0 resd Kept at its default value Bit 2 0 ADRLEN 0x3 rw SPI address length This field defines the number of bytes of the SPI Flash address ranging from one to four bytes 000 No address state 001 1 byte address 010 2 byte address 011 3 byte address 100 4 byte address Others Reserved When the address length is 0 the second dummy state period is not preset 28 4 3 Command word 2 CMD_W2 ...

Page 669: ...I write data excluding read data or read status read data return path the user must set write enable bit 1 for other SPI commands Note Write enable must be set to 1 in data write or Flash erase command The write enable must be set to 0 only in read data or read status command 0 Disabled 1 Enabled Bit 0 Reserved 0x0 resd Kept at its default value 28 4 5 Control register CTRL No wait states accessib...

Page 670: ...divider 000 Divided by 2 001 Divided by 4 010 Divided by 6 011 Divided by 8 100 Divided by 3 101 Divided by 5 110 Divided by 10 111 Divided by 12 28 4 6 AC timing register ACTR No wait states accessible by bytes half words and words Bit Register Reset value Type Description Bit 31 4 Reserved 0x0000 000 resd Kept at its default value Bit 3 0 CSDLY 0xF rw cs delay Indicates the time from inactive cs...

Page 671: ...ode The value is in terms of word The trigger value is the data in the TxFIFO 00 8 WORD 01 16 WORD 10 24 WORD 11 Reserved Bit 7 2 Reserved 0x00 resd Kept at its default value Bit 1 CMDIE 0x0 rw Command complete Interrupt enable 0 Command complete Interrupt disabled 1 Command complete Interrupt enabled Bit 0 DMAEN 0x0 rw DMA enable Note This bit must be disabled before moving from command based sla...

Page 672: ...4 byte address Bit 10 8 XIPR_OPMODE 0x0 rw XIP read Operation mode 000 Serial mode 001 Dual mode 010 Quad mode 011 Dual IO mode 100 Quad IO mode 101 DPI mode 110 QPI mode 111 Reserved Bit 7 0 XIPR_DUM2 0x00 rw XIP Read second dummy cycle The second dummy state is located between the address and data status excluding continuous read mode status The user can check if there is a dummy state between t...

Page 673: ...secutive addresses put a limit on the maximum data count DCNT in a single write operation Mode T When two consecutive data are written and the addresses are also continuous and the interval is less than a specified time TCNT then they are combined into one command Bit 30 24 XIPW_TCNT 0x0F rw This indicates the time counter that is used to judge time interval in mode T Value is in terms of sck_out ...

Page 674: ...f words and words Bit Register Reset value Type Description Bit 31 4 Reserved 0x0000 000 resd Kept at its default value Bit 3 CSTS 0x0 r Cache Status 0 Cache verified 1 Cache failed Bit 2 1 Reserved 0x0 resd Kept at its default value Bit 0 BYPASSC 0x0 rw Bypass Cache Function When this bit is set the high speed cache feature is deactivated and all read transfers do not check high speed cache 28 4 ...

Page 675: ...ly support AHB OKAY and ERROR responses HBUSREQ and HGRANT of AHB master interface are not supported Two AHB main interfaces for data transfer Support 8 channels Peripheral to memory memory to peripheral and memory to memory transfers Support hardware handshake Support 8 bit 16 bit and 32 bit data transfers Programmable amount of data to be transferred up to 65535 Programmable chain transmission P...

Page 676: ...DTH MWIDTH Data transfer mode PBURST MBURST Single transfer or burst transfer In non incrementing mode burst transfers of 4 8 or 16 beats are translated into 4 8 or 16 single transfers In direct mode PBURST and MBURST bits are forced to 0 single transfer mode Peripheral flow control PFCTRL If PFCTRL 1 peripheral flow control is used the value of the DMA_SxDTCNT register is forced to 0xFFFF The dma...

Page 677: ...A controller releases the acknowledge signal as well In non incrementing mode PINCM 0 burst transfers 4 8 or 16 beats are translated into 4 8 or 16 single transfers These data will be transferred by the main peripheral controller in a request acknowledge group In peripheral flow control mode PFCTRL 1 only a single transfer is present in a request acknowledge group 29 3 4 Arbiter When several chann...

Page 678: ...register When PWIDTH is not equal to MWIDTH a packing and unpacking mechanism is performed When the transfer size of the source data is less than that of the destination data the data is packed in FIFO before sending to the destination On the contrary if the transfer size of the source data is greater than that of the destination data the data is unpacked before sending to the destination PWIDTH M...

Page 679: ...yte lane 2 byte lane 1 byte lane 0 byte lane 3 Perpheral Address Field PINC 1 PSIZE BYTE 29 3 6 FIFO and threshold Each stream has its dedicated 4 word FIFO that is programmed with different threshold 1 4 1 2 3 4 or full The FTHSEL bit must match the MBURST bit otherwise a FIFO error FERR is generated while enabling a stream causing that a stream is automatically disabled FTHSEL 4 MBURST MWIDTH M ...

Page 680: ...ntinue to set DMA_SxDTCNT 0 write the descriptor address to the DMA_SxLLP and enable a stream After enabling a stream the memory controller in DMA issues a few AHB commands to load the descriptor from the main memory Figure 29 7 gives the descriptor format After loading descriptors that is CTRL and CNT PADDR and M0ADDR the DMA uses these bits for data transfers When a descriptor transaction is com...

Page 681: ...can perform the second iteration and read four data beats from the slave word address 0x8 0x9 0xA and 0xB byte address ranging from 0x20 to 0x2F The YCOUTNT bit has up to 8 iterations which is equal to 0x8 When both the YCOUTNT and XCOUNT bits become 0 it indicates that a total of 32 word data 8 iterations 4 beats have been read from the source memory Figure 29 9 Example of a 2D transfer source si...

Page 682: ... values must be two s complement PINCM and MINCM bits must be set to 1 incremented mode PFCTRL bit must be set to 0 PINCOS bit must be set to 0 Circular and dual buffer mode are not supported Linked table transfer is not supported 29 3 9 Errors Table 29 1 DMA error events Error events Transfer error AHB response error during DMA read write Write access to the current destination memory address reg...

Page 683: ...in the DMA_MUXCxCTRL register EXINT LINE is used as the trigger input for request generators and the synchronized input for requests 29 4 1 DMAMUX functional overview The DMAMUX consists of a request generator and a request multiplexer Each of the DMAMUX generator channel x has a GEN enable bit in the DMA_MUXGxCTR register The SIGSEL bit is used to select the trigger input of the DMAMUX generator ...

Page 684: ...R1_CH2 75 TMR5_CH4 107 SPI4_TX 12 SPI2_RX 44 TMR1_CH3 76 TMR5_OVERFLOW 108 reserved 13 SPI2_TX 45 TMR1_CH4 77 TMR5_TRIG 109 reserved 14 SPI3_RX 46 TMR1_OVERFLOW 78 reserved 110 I2S2_EXT_RX 15 SPI3_TX 47 TMR1_TRIG 79 reserved 111 I2S2_EXT_TX 16 I2C1_RX 48 TMR1_HALL 80 reserved 112 I2S3_EXT_RX 17 I2C1_TX 49 TMR8_CH1 81 reserved 113 I2S3_EXT_TX 18 I2C2_RX 50 TMR8_CH2 82 reserved 114 USART6_RX 19 I2C2...

Page 685: ...7 DMA_MUXevt2 25 reserved 2 exint_gpio 2 10 exint_gpio 10 18 DMA_MUXevt3 26 reserved 3 exint_gpio 3 11 exint_gpio 11 19 DMA_MUXevt4 27 reserved 4 exint_gpio 4 12 exint_gpio 12 20 DMA_MUXevt5 28 reserved 5 exint_gpio 5 13 exint_gpio 13 21 DMA_MUXevt6 29 reserved 6 exint_gpio 6 14 exint_gpio 14 22 DMA_MUXevt7 30 reserved 7 exint_gpio 7 15 exint_gpio 15 23 DMA_MUXevt8 31 reserved 29 4 2 DMAMUX overfl...

Page 686: ..._req n syncx mux_syncx chx_mux_req mux_req_cnt mux_evtx CLK 2 1 0 2 mux_syncp DMA request served SYNCEN 1 EVTGEN 1 SPOL 01 REQCNT 2 Figure 29 13 DMAMUX event generation 1 0 2 1 0 2 Selected all_req n CLK chx_mux_req mux_req_cnt 2 mux_evtx SYNCEN EVTGEN SYNCEN 0 EVTGEN 1 REQCNT 2 ...

Page 687: ...0000 EDMA_S2CTRL 0x28 0x0000 0000 EDMA_S2DTCNT 0x2c 0x0000 0000 EDMA_S2PADDR 0x30 0x0000 0000 EDMA_S2M0ADDR 0x34 0x0000 0000 EDMA_S2M1ADDR 0x38 0x0000 0000 EDMA_S2FCTRL 0x3c 0x0000 0000 EDMA_S3CTRL 0x40 0x0000 0000 EDMA_S3DTCNT 0x44 0x0000 0000 EDMA_S3PADDR 0x48 0x0000 0000 EDMA_S3M0ADDR 0x4c 0x0000 0000 EDMA_S3M1ADDR 0x50 0x0000 0000 EDMA_S3FCTRL 0x54 0x0000 0000 EDMA_S4CTRL 0x58 0x0000 0000 EDMA...

Page 688: ...EDMA_LLCTRL 0xd0 0x0000 0000 EDMA_S1LLP 0xd4 0x0000 0000 EDMA_S2LLP 0xd8 0x0000 0000 EDMA_S3LLP 0xdc 0x0000 0000 EDMA_S4LLP 0xe0 0x0000 0000 EDMA_S5LLP 0xe4 0x0000 0000 EDMA_S6LLP 0xe8 0x0000 0000 EDMA_S7LLP 0xec 0x0000 0000 EDMA_S8LLP 0xf0 0x0000 0000 EDMA_S2DCTRL 0xf4 0x0000 0000 EDMA_S12DCNT 0xf8 0x0000 0000 EDMA_S1STRIDE 0xfc 0x0000 0000 EDMA_S22DCNT 0x100 0x0000 0000 EDMA_S2STRIDE 0x104 0x000...

Page 689: ...t state accessible by bytes half words or words Bit Register Reset value Type Description Bit 31 28 Reserved 0x0 resd Kept at its default value Bit 27 FDTF4 0x0 ro Stream4 full data transfer complete interrupt flag Bit 26 HDTF4 0x0 ro Stream4 half data transfer complete interrupt flag Bit 25 DTERRF4 0x0 ro Stream4 transfer error interrupt flag Bit 24 DMERRF4 0x0 ro Stream4 direct mode error interr...

Page 690: ...MA_STS2 Access 0 wait state accessible by bytes half words or words Bit Register Reset value Type Description Bit 31 28 Reserved 0x0 resd Kept at its default value Bit 27 FDTF8 0x0 ro Stream6 full data transfer complete interrupt flag Bit 26 HDTF8 0x0 ro Stream8 half transfer complete interrupt flag Bit 25 DTERRF8 0x0 ro Stream8 transfer error interrupt flag Bit 24 DMERRF8 0x0 ro Stream8 direct mo...

Page 691: ...d Kept at its default value Bit 27 FDTFC4 0x0 w Stream4 clear transfer complete interrupt flag Bit 26 HDTFC4 0x0 w Stream4 clear half transfer complete interrupt flag Bit 25 DTERRFC4 0x0 w Stream4 clear error interrupt flag Bit 24 DMERRFC4 0x0 w Steam4 clear direct mode error interrupt flag Bit 23 Reserved 0x0 resd Kept at its default value Bit 22 FERRFC4 0x0 w Stream4 clear fifo error interrupt f...

Page 692: ...RRFC8 0x0 w Stream8 clear error interrupt flag Bit 24 DMERRFC8 0x0 w Steam8 clear direct mode error interrupt flag Bit 23 Reserved 0x0 resd Kept at its default value Bit 22 FERRFC8 0x0 w Stream8 clear fifo error interrupt flag Bit 21 FDTFC7 0x0 w Stream7 clear transfer complete interrupt flag Bit 20 HDTFC7 0x0 w Stream7 clear half transfer complete interrupt flag Bit 19 DTERRFC7 0x0 w Stream7 clea...

Page 693: ...ment burst This field is forced to 00 when SEN 1 Note This field can be written only when SEN 0 Bit 22 21 PBURST 0x0 rw Peripheral burst transfer configuration This field defines the type of peripheral transfers 00 Single transfer 01 INCR4 4 beat increment burst 10 INCR8 beat increment burst 11 INCR16 16 beat increment burst This field is forced to 00 when SEN 1 Note This field can be written only...

Page 694: ...ved This field can be written only when SEN 0 Bit 10 MINCM 0x0 rw Memory increment mode 0 Memory address pointer is fixed 1 Memory address pointer is incremented This bit can be written only when SEN 0 Bit 9 PINCM 0x0 rw peripheral increment mode 0 Peripheral address pointer is fixed 1 Peripheral address pointer is incremented This bit can be written only when SEN 0 Bit 8 LM 0x0 rw Loop mode 0 Loo...

Page 695: ...words or words Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit15 0 CNT 0x0000 rw Number of data to be transferred 0 65535 This register can be written only when SEN 0 This register is read only when SEN 1 indicating the remaining data to be transmitted This register is decremented after each transfer Typically this register remains 0 after the...

Page 696: ...l buffer mode and CM 1 29 5 10DMA stream x FIFO control register DMA_SxFCTRL x 1 8 Access 0 wait state accessible by bytes half words or words Bit Register Reset value Type Description Bit 31 8 Reserved 0x0000 00 resd Kept at its default value Bit 7 FERRIEN 0x0 rw FIFO error interrupt enable 0 FIFO error interrupt disabled 1 FIFO error interrupt enabled Bit 6 Reserved 0x0 resd Kept at its default ...

Page 697: ...it Register Reset value Type Description Bit 31 0 LLP 0x0000 0000 rw link list pointer After the completion of the current descriptor the flow controller uses this pointer as a target address to read the descriptor 29 5 13DMA 2D transfer control register DMA_S2DCTRL Access 0 wait state accessible by bytes half words or words Bit Register Reset value Type Description Bit 31 8 Reserved 0x0 resd Kept...

Page 698: ...0 0 0x7FFF 32767 0x8000 32768 0x8001 32767 0xFFFF 1 The SRC value is in terms of byte address For example if the source stride is 0x8 the source byte address is added with 0x8 before the next iteration SRCSTDbit 1 0 must be 00 for the size of the source position remains word 29 5 16DMA synchronization enable DMA_SYNCEN Access 0 wait state accessible by bytes half words or words Bit Register Reset ...

Page 699: ...d defines the number of DMA requests after synchronization events and or before synchronization events This field are reserved only if SYNCEN and EVTGEN both are 0 Bit 18 17 SYNCPOL 0x0 rw Synchronization polarity Defines the polarity of the selected synchronization input 0x0 No event 0x1 Rising edge 0x2 Falling edge 0x3 Rising and falling edge Bit 16 SYNCEN 0x0 rw Synchronization enable 0 Synchro...

Page 700: ...r overrun interrupt enable 0 Interrupt disabled 1 Interrupt enabled Bit 7 5 Reserved 0x0 resd Kept at its default value Bit 4 0 SIGSEL 0x00 rw Signal select This field is used to select DMA signal for DMA request generation 29 5 20DMAMUX synchronization interrupt status register DMA_MUXSYNCSTS Access 0 wait state accessible by bytes half words or words Bit Register Reset value Type Description Bit...

Page 701: ...0 ro Trigger overrun interrupt flag This bit is set when a new trigger event occurs while the DMA request count is below the GNBREQ 29 5 23DMAMUX generator interrupt clear flag register DMA_ MUXGCLR Access 0 wait state accessible by bytes half words or words Bit Register Reset value Type Description Bit 31 8 Reserved 0x0000 000 resd Kept at its default value Bit 7 0 TRGOVFC 0x00 rw1c Trigger overr...

Page 702: ...nd FCLK to continue to work In DeepSleep mode HICK oscillator is enabled to feed FCLK and HCLK There are several ID codes inside the MCU which is accessible by the debugger using the DEBUG_IDCODE at address 0xE0042000 It is part of the DEBUG and is mapped on the external PPB bus These codes are accessible using the JTAG debug port or the SWD debug port or by the user software They are even accessi...

Page 703: ...B LQFP48 0x7008_334A AT32F435CGT7 1024KB LQFP48 0x7008_324B AT32F435CCT7 256KB LQFP48 0x7008_454C AT32F435CMU7 4032KB QFN48 0x7008_334D AT32F435CGU7 1024KB QFN48 0x7008_324E AT32F435CCU7 256KB QFN48 0x7008_454F AT32F437ZMT7 4032KB LQFP144 0x7008_3350 AT32F437ZGT7 1024KB LQFP144 0x7008_3251 AT32F437ZCT7 256KB LQFP144 0x7008_4552 AT32F437VMT7 4032KB LQFP100 0x7008_3353 AT32F437VGT7 1024KB LQFP100 0x...

Page 704: ...et by POR Reset not reset by system reset It can be written by the debugger under reset Bit Register Reset value Type Description Bit 31 29 Reserved 0x0 resd Kept at its default value Bit 28 I2C3_SMBUS_TIMEO UT 0x0 rw I2C3 pause control bit 0 I2C3 SMBUS timeout control works normally 1 I2C3 SMBUS timeout control stops running Bit 27 I2C2_SMBUS_TIMEO UT 0x0 rw I2C2 pause control bit 0 I2C2 SMBUS ti...

Page 705: ...y 1 TMR6 stops running Bit 3 TMR5_PAUSE 0x0 rw TMR5 pause control bit 0 TMR5 works normally 1 TMR5 stops running Bit 2 TMR4_PAUSE 0x0 rw TMR4 pause control bit 0 TMR4 works normally 1 TMR4 stops running Bit 1 TMR3_PAUSE 0x0 rw TMR3 pause control bit 0 TMR3 works normally 1 TMR3 stops running Bit 0 TMR2_PAUSE 0x0 rw TMR2 pause control bit 0 TMR2 works normally 1 TMR2 stops running 30 4 4 DEBUG APB2...

Page 706: ...2 stops running 30 4 5 MCU SERIES ID register DEBUG_ SER_ID MCU_SIE_ID register is used to identify MCU part number and its revision code The DEBUG_IDCODE register is mapped on the external PPB bus This register is asynchronously reset by POR Reset not reset by system reset This code is accessible by the JTAG debug port or SW debug port or by the user code Bit Register Reset value Type Description...

Page 707: ...ed Section 13 2 6 DMA transfer 4 Updated Section 11 7 2 Control register2 I2C_CTRL2 5 Updated Figure 24 2 6 Updated Table 6 2 7 Updated Table 24 31 8 Updated Figure 1 1 9 Updated Section 20 6 7 Error management 10 Updated Section 20 7 CAN registers 11 Updated Section 24 7 1 5 SRAM NOR Flash extra timing register x XMC_EXTx x 1 2 3 4 12 Updated 11 7 1 Control register1 I2C_CTRL1 2022 11 11 2 03 1 U...

Page 708: ...nding legal situation in any injudical districts or infringement of any patent copyright or other intellectual property right ARTERY s products are not designed for the following purposes and thus not intended for the following uses A Applications that have specific requirements on safety for example life support applications active implant devices or systems that have specific requirements on pro...

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