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AT32F435/437
Series Reference Manual
2022.11.11
Page 231
Rev 2.03
Figure 13-13 TI mode continous transfer with dummy CLK
SCK
MISO
CS
MOSI
MSB
LSB
MSB
LSB
dumm
y
Write the to-be-transmitted data
When the to-be-transmitted data is written after the falling SCK edge corresponding to the last data of
the current transmit frame, the host always issues a valid SCK clock after 1T SCK + 4T PCLK. If the
slave still does not detect a valid CS pulse at the end of the current data reception, it disables MISO
output after 1/2T SCK + 3T PCLK to control MISO floating.
Figure 13-14 TI mode continous transfer with dummy CLK
SCK
Slave
MISO
CS
MSB
LSB MSB
LSB
1/2T SCK+3T
PCLK
1T SCK+4T PCLK
Hiz
13.2.12 Interrupts
Figure 13-15 SPI interrupts
RDBF
RDBFIE
TDBE
TDBEIE
ROERR
MMERR
CCERR
ERRIE
SPI interrupt
13.2.13 IO pin control
Usually, the SPI is connected to external devices through four pins.
MISO: Master In/Slave Out. The pin receives data in master mode, and transmits data in slave
mode.
MOSI: Master Out/Slave In. The pin transmits data in master mode, and receives data in slave
mode.
SCK: SPI communication clock. The pin serves as output in master mode, and input in slave
mode.
CS: Chip Select. This is an optional pin which selects master/slave mode.
Note: Some of SPI1/I
2
S1 and SPI3/I
2
S3 are shared with JTAG pins
(SPIx_CS/I2Sx_WS shared with JTDI, SPIx_SCK/I2Sx_CK with JTDO), so
these pins are not controlled by IO controller, and they are used as JTAG by
default after each reset. To configure them as SPIx/I
2
Sx, the JTAG should be
disabled (during debugging) and switched to SWD interface, or both the JTAG
and SWD are disabled (during normal run)