Xerox ColorQube 9303 Series, Руководство по обслуживанию

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February 2013
8-21 ColorQube® 9303 Family
Principles of Operation
System Communications
Communications
This section describes the system-wide Low-voltage differential signaling (LVDS) serial com-
munications links.
LVDS Serial Data / Control
The serial I/O bus provides communication between the IME controller board, drum driver
board, marking unit driver board, media path driver board, individual printhead driver boards,
and system controller boards. Each of these interfaces implements one dedicated serial path.
The serial bus is comprised of differential clock, differential receive, and differential transmit
pairs. These are generically called clk/clk*, rx/rx*, and tx/tx*. It should be noted that each inter-
face signal group may differ slightly; for instance, the system controller has only a transmit path
to the IME Controller.
The system controller communicates control information to each of the above interfaces over
the serial bus, and also accepts return data. This information is organized in data frames. Each
frame contains 64 time slots, one serial clock in duration each and beginning with frame signal
encoded throughout the frame set. The LVDS switching levels are centered 1.25V,
with each side of the differential pair switching b1.1V and +1.4V.
In the LVDS scheme, the logic state of the transmitted bit is represented by the difference
between Vout+ and Vout-, with a 1 represented by a positive difference (greater than +100mV)
of the two, and a 0 represented by a negative difference (greater than -100mV) of the two. This
scheme has the advantage of common-mode noise rejection, since such noise will be filtered
out by the signal differential.
Image Data
The objective of this interface is to provide a high bandwidth path to transfer images to the IME
in the format and at the time required. Image data is sent by a four channel LVDS interface.
Three of the channels transfer 6 bits per clock cycle. The fourth channel is a 33.3 MHz clock.
The start of serial frame is indicated by the rising edge of the clock. The receiver must create a
6x clock (200MHz) from the LVDS clock to clock in the six data bits on each channel. They are
then combined to form an 18 bit serial frame.
Since the image data is post processed on the IME controller board, it does not need to be
transmitted in sync with marking unit activity. Rather, an entire image is transmitted at approxi-
mately four times the average data bandwidth to minimize the transfer latency to improve
FCOT/FPOT. The entire interface is unidirectional (output from SBC, input to IME). Any status
and setup information is communicated over the command interface.
High Speed Communications
The communications link between the IME controller board and the media path driver (MPD)
board is a standard ColorQube fast link. Originally for LP1 this link was based on a 66.3 MHz
clock. Data frames of 1s were sent between the IME controller and the MPD. Each data frame
contained 64 slots of data. These data frames contained drive signals, sensor signals etc. to
and from the MPD.
Low Speed Communications
For satellite boards of the MPD, and various peripherals, a slower link of 1.036 MHz is used.
Devices on the slow link decode their data on the positive edge of the 1.036MHz clock. Data is
transferred to the media path driver on the positive edge of the 1.036MHz clock. The actual
decoding of data received occurs on IME controller board.
Power On Self Test (POST)
The ColorQube Power On Self Test (POST) checks the following:
• Communication between the main IME PWBs including:
– Single board controller PWB, PL 3.11 Item 13 .
– IME controller PWB, PL 92.10 Item 1
– Media path driver PWB, PL 1.15 Item 5
– Marking unit driver PWB, PL 92.10 Item 4
• The system memory and NVRAM.
• Compatible software and firmware versions are installed.
• Power supply to the main IME components.
The POST runs automatically as part of the machine power-on sequence and is performed
before higher level machine functions, such as the user interface (UI), are operational. The
POST can therefore be used to diagnose faults on a machine with an unresponsive UI which
prevents access to the fault lists and service messages.
The POST results are displayed using the LED’s on the front of the IME controller PWB, the
media path driver PWB and the single board controller PWB. Refer to
OF 16 POST Error RAP
for details of the LED locations.
LEDs on the IME controller PWB:
• ENG OK (green, DS302) - Displays IME firmware status.
• ENG error (red, DS301) - Displays IME firmware error blink codes, the first digit is 3 or 4.
• Cable error (red, DS604) - Displays status of major cables in the IME and of the -12V
needed for the printhead PWBs.
• CPU error (red, DS605) - Displays IME operating system status and error blink codes, the
first digit is 2.
LED’s on the media path driver PWB:
• IME OK (green, DS801) - Displays IME firmware status.
• IME error (red, DS802) - Displays IME firmware error blink codes.
If a loss of communication to the media path driver PWB occurs, only the IME controller PWB
LEDs displays POST results.
The 7-segment LED display unit on the rear of the machine attached to the single board con-
troller PWB. The LED display should show just a pulsing decimal point when the machine
boots correctly. The main codes are displayed for short periods of time during power up
depending on how long each test takes. If any code is left displayed during power up and the
machine appears not to have powered on correctly then this should point to the problem com-
ponent.
Refer to OF 16 POST Error RAP for information on interpreting the POST error codes.