Registers
819
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.12.1 SD_VENC_pid Register (offset = 0h) [reset = 4FFF0000h]
SD_VENC_pid is shown in
and described in
.
Revision Register
Figure 1-496. SD_VENC_pid Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PID
R-4FFF0000h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-412. SD_VENC_pid Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
PID
R
4FFF0000h
Revision ID.