Texas Instruments DM38x DaVinci, Руководство пользователя

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Internal Modules
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174 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.2.8.2.18.3 vsync and actvid Input Signals
Figure 1-123 shows vsync from Group 1 and actvid from Group 2 being used. Set
USE_ACTVID_HSYNC_N=’1’ and DISCRETE_BASIC_MODE=’1’. Again, since VIP is not aware of when
VBI data starts and ends, all lines, including both vertical ancillary and active video, will appear in the
memory. Lines starting after an inactive to active transition on vsync will delineate a start of frame. Lines
are denoted by an inactive to active transition of actvid. Pixel will be saved only when actvid is active.
Note that vsync must transition active between the actvid delineated data. vsync cannot transition active
when actvid is active.
Figure 1-123. vsync and actvid Input Signals
1.2.8.2.18.4 vblank and hsync Input Signals
Figure 1-124 shows vblank from Group 1 and hsync from Group 2 being used. In this scenario, set
USE_ACTVID_HSYNC_N=’0’ and DISCRETE_BASIC_MODE=’0’. Again, since VIP is aware of the start
and end of vertical blanking interval start and end, vertical ancillary and active video data will appear in
different memory buffers. Lines starting from inactive to active transition on vblank will delineate a start of
the frame. When vblank is active, all data elements on pixel clock’s active edge will appear in ancillary
data buffer and when vblank is inactive, all data elements on pixel clock’s active edge will appear in video
data buffer.
Figure 1-124. vblank and hsync Input Signals