Registers
322
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.1.6
CHR_US_reg5 Register (offset = 18h) [reset = 0h]
CHR_US_reg5 is shown in
and described in
.
Upsampling Coeffs
Figure 1-216. CHR_US_reg5 Register
31
30
29
28
27
26
25
24
ANCHOR_FID1_C2
R/W-0h
23
22
21
20
19
18
17
16
ANCHOR_FID1_C2
Reserved
R/W-0h
R-0h
15
14
13
12
11
10
9
8
ANCHOR_FID1_C3
R/W-0h
7
6
5
4
3
2
1
0
ANCHOR_FID1_C3
Reserved
R/W-0h
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-122. CHR_US_reg5 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-18
ANCHOR_FID1_C2
R/W
0h
C2 coefficient for Anchor Pixel. Used when field_id = 1
17-16
Reserved
R
0h
Reserved
15-2
ANCHOR_FID1_C3
R/W
0h
C3 coefficient for Anchor Pixel. Used when field_id = 1
1-0
Reserved
R
0h
Reserved