(
)
(
)
(
)
4095
10
1000
2089
14
1400
0
Y
LSB
A
mV
mV
S
=
×
×
=
=
1
0
255
0
308
60
157
1
152
229
77
64
270
52
322
Y
Y
G
S
U
A
B
V
R
G
B
R
=
•
•
+
=
−
−
−
−
M
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
4095
10
1000
92.5%
1932.6
14
1400
4095
10
1000
7.5%
157
14
1400
4095
4
1000
836
14
1400
Y
LSB
A
mV
mV
LSB
S
mV
mV
LSB
Sync
mV
mV
=
×
×
×
=
=
×
×
×
=
=
×
×
=
1
0
255
0
285
55
145
157
1
140
211
71
0
64
250
48
298
0
Y
Y
G
S
U
A
B
V
R
G
B
R
=
•
•
+
=
−
−
+
−
−
M
Internal Modules
112
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
Example 1-1. Full-range RGB [0…255] to YUV 10:4 Picture Sync Ratio with 7.5% Setup
In this example, it is assumed that DAC is configured to have maximum amplitude of 1400 mV.
This coefficient set is preset by default for the CVBS CSC registers.
Example 1-2. Full-range RGB to YUV 10:4 Picture Sync Ratio with Zero Setup