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Registers
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470 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
Table 1-225. VPDMA_int0_channel0_int_stat Register Field Descriptions (continued)
Bit Field Type Reset Description
18 INT_STAT_SCALER_LU
MA W 0h
The last write DMA transaction has completed for channel
scaler_luma. All data from the channel has been sent and received
by the external memory. If a new channel has not been setup for the
client then the client will be fully empty at this point. This event will
cause a one to be set in this register until cleared by software. Write
a 1 to this field to clear the value.
17 INT_STAT_HQ_SCALER W 0h
The last write DMA transaction has completed for channel hq_scaler.
All data from the channel has been sent and received by the external
memory. If a new channel has not been setup for the client
dei_sc_out then the client will be fully empty at this point. This event
will cause a one to be set in this register until cleared by software.
Write a 1 to this field to clear the value.
16 Reserved R 0h
15 INT_STAT_HQ_MV_OUT W 0h
The last write DMA transaction has completed for channel
hq_mv_out. All data from the channel has been sent and received by
the external memory. If a new channel has not been setup for the
client dei_hq_mv_out then the client will be fully empty at this point.
This event will cause a one to be set in this register until cleared by
software. Write a 1 to this field to clear the value.
14-13 Reserved R 0h
12 INT_STAT_HQ_MV W 0h
The last read DMA transaction has occurred for channel hq_mv and
the channel is free to be updated for the next transfer. This will fire
before the destination has received the data as it will have just been
stored in the internal buffer. The client dei_hq_mv_in will now accept
a new descriptor from the List Manager. This event will cause a one
to be set in this register until cleared by software. Write a 1 to this
field to clear the value.
11-6 Reserved R 0h
5 INT_STAT_HQ_VID3_CH
ROMA W 0h
The last read DMA transaction has occurred for channel
hq_vid3_chroma and the channel is free to be updated for the next
transfer. This will fire before the destination has received the data as
it will have just been stored in the internal buffer. The client
dei_3_chroma will now accept a new descriptor from the List
Manager. This event will cause a one to be set in this register until
cleared by software. Write a 1 to this field to clear the value.
4 INT_STAT_HQ_VID3_LU
MA W 0h
The last read DMA transaction has occurred for channel
hq_vid3_luma and the channel is free to be updated for the next
transfer. This will fire before the destination has received the data as
it will have just been stored in the internal buffer. The client
dei_3_luma will now accept a new descriptor from the List Manager.
This event will cause a one to be set in this register until cleared by
software. Write a 1 to this field to clear the value.
3 INT_STAT_HQ_VID2_CH
ROMA W 0h
The last read DMA transaction has occurred for channel
hq_vid2_chroma and the channel is free to be updated for the next
transfer. This will fire before the destination has received the data as
it will have just been stored in the internal buffer. The client
dei_2_chroma will now accept a new descriptor from the List
Manager. This event will cause a one to be set in this register until
cleared by software. Write a 1 to this field to clear the value.
2 INT_STAT_HQ_VID2_LU
MA W 0h
The last read DMA transaction has occurred for channel
hq_vid2_luma and the channel is free to be updated for the next
transfer. This will fire before the destination has received the data as
it will have just been stored in the internal buffer. The client
dei_2_luma will now accept a new descriptor from the List Manager.
This event will cause a one to be set in this register until cleared by
software. Write a 1 to this field to clear the value.