Registers
895
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
Table 1-484. VIP_PARSER_port_b Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
22
DISCRETE_BASIC_MOD
E
R/W
0h
This register is valid for Discrete Sync mode only.
0 = Normal Discrete Mode.
Hsync Style Capture operates as follows:
- Captures line starting from HSYNC inactive to active condition.
- VSYNC determined by sync window.
- FID can be determined by VSYNC skew or captured from pin at
first pixel in first line.
ACTVID style capture works as follows:
- Captures line during contiguous ACTVID envelope.
- VSYNC is captured at the first pixel in each line.
- FID is captured on first pixel of ACTVID window.
1 = Basic Discrete Mode.
When using hsync with Hsync Style Capture operates as follows:
- The last line of active video ends on the pixel clock cycle where
VSYNC transitions from inactive to active.
- FID pin value is captured on this cycle and is used for the next
field.
- FID detection by VSYNC skew is not allowed.
ACTVID style capture works as follows:
- VSYNC is expected to transition from inactive to active between
ACTVID window.
- This VSYNC transition allows the next line in an ACTVID envelope
to be sent to a new VPDMA buffer.
- FID value is determined by the FID pin value on the cycle where
VSYNC transitions from inactive to active.
In basic discrete mode, there is no Vertical Ancillary Data. Therefore,
VPDMA descriptors should not use Ancillary Data channels.
21-16
FID_SKEW_PRECOUNT
R/W
0h
Discrete Sync Only pre count value when using vsync skew in FID
determination
15
USE_ACTVID_HSYNC_N
R/W
0h
Discrete Sync Only
0 = Use HSYNC style line capture
1 = Use ACTVID style line capture
14
FID_DETECT_MODE
R/W
0h
Discrete Sync Only
0 = Take FID from pin
1 = FID is determined by VSYNC skew
13
ACTVID_POLARITY
R/W
0h
Discrete Sync Only
0 = ACTVID is active low
1 = ACTVID is active high
12
VSYNC_POLARITY
R/W
0h
Discrete Sync Only
0 = VSYNC is active low
1 = VSYNC is active high
11
HSYNC_POLARITY
R/W
0h
Discrete Sync Only
0 = HSYNC is active low
1 = HSYNC is active high
10
PIXCLK_EDGE_POLARIT
Y
R/W
0h
0 = Rising Edge is active PIXCLK edge
1 = Falling Edge is active PIXCLK edge
9
FID_POLARITY
R/W
0h
0 = Keep FID as found
1 = Invert Determined Value of FID
Value on FID pin in discrete sync or value of "F-bit" in embedded
sync indicates whether a field is EVEN or ODD (time-domain).
However modules in HDVPSS follow convention (top/bottom) as
specified in the table of HDVPSS Acronyms. As a result, fid_polarity
needs to be set appropriately. Typically, this will result in different
configuration for fid_polarity between PAL and NTSC modes.
