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Registers
529 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.3.8.33 VPDMA_int1_channel0_int_stat Register (offset = 90h) [reset = 0h]
VPDMA_int1_channel0_int_stat is shown in Figure 1-333 and described in Table 1-245 .
Figure 1-333. VPDMA_int1_channel0_int_stat Register
31 30 29 28 27 26 25 24
INT_STAT_GRPX3 INT_STAT_GRPX2 INT_STAT_GRPX1 INT_STAT_SCALER_
OUT
Reserved
W-0h W-0h W-0h W-0h R-0h
23 22 21 20 19 18 17 16
Reserved INT_STAT_SCALER_
CHROMA
INT_STAT_SCALER_
LUMA
INT_STAT_HQ_SCAL
ER
Reserved
R-0h W-0h W-0h W-0h R-0h
15 14 13 12 11 10 9 8
INT_STAT_HQ_MV_
OUT
Reserved INT_STAT_HQ_MV Reserved
W-0h R-0h W-0h R-0h
7 6 5 4 3 2 1 0
Reserved INT_STAT_HQ_VID3
_CHROMA
INT_STAT_HQ_VID3
_LUMA
INT_STAT_HQ_VID2
_CHROMA
INT_STAT_HQ_VID2
_LUMA
INT_STAT_HQ_VID1
_CHROMA
INT_STAT_HQ_VID1
_LUMA
R-0h W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 1-245. VPDMA_int1_channel0_int_stat Register Field Descriptions
Bit Field Type Reset Description
31 INT_STAT_GRPX3 W 0h
The last read DMA transaction has occurred for channel grpx3 and
the channel is free to be updated for the next transfer. This will fire
before the destination has received the data as it will have just been
stored in the internal buffer. The client grpx3_data will now accept a
new descriptor from the List Manager. This event will cause a one to
be set in this register until cleared by software. Write a 1 to this field
to clear the value.
30 INT_STAT_GRPX2 W 0h
The last read DMA transaction has occurred for channel grpx2 and
the channel is free to be updated for the next transfer. This will fire
before the destination has received the data as it will have just been
stored in the internal buffer. The client grpx2_data will now accept a
new descriptor from the List Manager. This event will cause a one to
be set in this register until cleared by software. Write a 1 to this field
to clear the value.
29 INT_STAT_GRPX1 W 0h
The last read DMA transaction has occurred for channel grpx1 and
the channel is free to be updated for the next transfer. This will fire
before the destination has received the data as it will have just been
stored in the internal buffer. The client grpx1_data will now accept a
new descriptor from the List Manager. This event will cause a one to
be set in this register until cleared by software. Write a 1 to this field
to clear the value.
28 INT_STAT_SCALER_OU
T W 0h
The last write DMA transaction has completed for channel
scaler_out. All data from the channel has been sent and received by
the external memory. If a new channel has not been setup for the
client sc_out then the client will be fully empty at this point. This
event will cause a one to be set in this register until cleared by
software. Write a 1 to this field to clear the value.
27-20 Reserved R 0h
19 INT_STAT_SCALER_CH
ROMA W 0h
The last write DMA transaction has completed for channel
scaler_chroma. All data from the channel has been sent and
received by the external memory. If a new channel has not been
setup for the client then the client will be fully empty at this point.
This event will cause a one to be set in this register until cleared by
software. Write a 1 to this field to clear the value.