Internal Modules
169
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.2.8.2.11 VDET Interrupt
For Line Multiplexing Embedded Sync mode only, the Meta Data Header includes a Video Detect (VDET)
flag. The TVP5158 sets this VDET flag whenever NTSC or PAL sync is found. Some other external
devices using Line Multiplexing mode may not use VDET. However, when VDET changes, a VDET
interrupt is issued to the DSS interrupt controller. Each Pixel Clock Input Domain has a separate VDET
interrupt.
The VDET status register is comprised of 32 bits, each bit representing the value of the VDET flag found
in the Meta Data of the Channel ID. Bit 0 is the VDET value from Channel ID 0, Bit 1is is VDET value from
Channel ID 1, etc. There is a separate status register for each Pixel Input Clock Domain.
In Line Mux mode, the meta-data field defining the srcnum is 5 bits wide. The TVP5158 spec only defines
the last three bits of this field and the upper two bits are reserved. When set to ‘1’, the
cfg_tvp5158_chan_id_type register tells the VIP Parser to ignore the top two bits of the field any only use
the lower three bits, giving a maximum of eight srcnums. This bit should always be set to '1' in TI Line Mux
mode.
1.2.8.2.12 Source Video Size
These status registers provide the size of the last active video frame in 16 different input sources per port.
There is no interrupt activated on the change in the source size in any of the input sources. These read-
only registers only inform the application of the width and the height of the last active field or frame
associated with each channel ID.
1.2.8.2.13 Clipping
The source for the clipping feature can be either embedded sync or discrete sync. Embedded sync
streams use 2 reserved codewords as sync codes, 0x00 and 0xFF. These sync codes define different
regions in the incoming data. Discrete sync streams have no limitation on the allowed quantization values.
All 8 bits, from 0x00 to 0xFF are legal quantization values.
Suppose the input is discrete sync and the device converts the discrete sync raw video into a embedded
sync stream (by adding appropriate embedded sync headers) and stores it on the network or hard disk. In
this case, the processor checks every raw video byte to ensure that the reserved 0x00 and 0xFF
codewords are not used in the raw video before the stream is saved. Otherwise, when the stored stream
is read back by some device as an embedded sync stream, illegal codes are found.
The hardware has the capability to clip illegal codewords into legal ones. This clipping is only needed for
discrete sync sourced inputs to the HDVPSS VIP module.
Embedded sync sourced input streams do not need to be clipped as they are presumably already
following the rules for embedded sync.
For the embedded sync interface, input values 0x00 and 0xFF are reserved for the sync detection, so
these values cannot be used in the rest of the system. The VIP Parser supports one configuration bit that,
when enabled, changes all 0x00 to 0x01 and 0xFF to 0xFE in the vertical ancillary data. Another
configuration bit, when enabled, changes all 0x00 to 0x01 and 0xFF to 0xFE in the active video portion of
the input picture.
Note that if the clipping is enabled for ancillary data, the post processing software will never be able to find
a data packet sync header, since the 00-FF-FF sequence will be changed to 01-FE-FE.
For 24- bit YUV, clipping is done on each 8 bit channel. If data[23:16]==0xFF, the clipped value will be
0xFE. If data[23:16]==0x00, the clipped value will be 0x01. Likewise, clipping is done for data bit ranges
15:8 and 7:0