Texas Instruments DM38x DaVinci, Руководство пользователя

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Internal Modules
173 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.2.8.2.18.1 vsync and hblank Input Signals
Figure 1-121 shows vsync from Group 1 and hblank from Group 2 being used. Set
USE_ACTVID_HSYNC_N=’0’ and DISCRETE_BASIC_MODE=’1’.
Also, since VIP is not aware of vertical blanking interval start and end, all lines, including both vertical
ancillary and active video, will appear in the memory. Lines starting after an inactive to active transition on
vsync will delineate a start of frame. Every data element on the Pixel clock’s active edge will be stored in
the Active Video Buffer.
Note that the vsync signal cannot transition active on the same cycle that hsync transitions active for fast
pixel clock rates, since a system clock cycle is needed to insert a new frame indicator into the frame
buffer.
Figure 1-121. vsync and hblank Input Signals
1.2.8.2.18.2 vsync and hsync Input Signals
Figure 1-122 shows vsync from Group 1 and hsync from Group 2 being used. Set
USE_ACTVID_HSYNC_N=’0’ and DISCRETE_BASIC_MODE=’1’. Since the VIP is not aware of when VBI
data starts and ends, all lines, including both vertical ancillary and active video, will appear in the memory.
Lines starting after an inactive to active transition on vsync will delineate a start of frame. Every data
element on the Pixel clock’s active edge will be stored in the Active Video Buffer. Note that this scenario is
the same as the vsync and hblank.
Like the vsync and hblank case, it also holds true that the vsync signal cannot transition active on the
same cycle that hsync transitions active for fast pixelclock rates since a system clock cycle is needed to
insert a new frame indicator into the framebuffer.
Figure 1-122. vsync and hsync Input Signals