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394 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.3.7.14 intc_intr1_status_ena1 Register (offset = 4Ch) [reset = 0h]
intc_intr1_status_ena1 is shown in Figure 1-270 and described in Table 1-181 .
Interrupt1 Enabled Register 1
Figure 1-270. intc_intr1_status_ena1 Register
31 30 29 28 27 26 25 24
Reserved VIP2_CHR_DS_2_UV
_ERR_INT_ENA
VIP2_CHR_DS_1_UV
_ERR_INT_ENA
R-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
VIP1_CHR_DS_2_UV
_ERR_INT_ENA
VIP1_CHR_DS_1_UV
_ERR_INT_ENA
NF_CHR_DS_UV_ER
R_INT_ENA
COMP_ERR_INT_EN
A
GRPX3_INT_ENA GRPX2_INT_ENA GRPX1_INT_ENA DEI_ERROR_INT_EN
A
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
VPDMA_INT1_CLIEN
T_ENA
VPDMA_INT1_CHAN
NEL_GROUP6_ENA
VPDMA_INT1_CHAN
NEL_GROUP5_ENA
VPDMA_INT1_CHAN
NEL_GROUP4_ENA
VPDMA_INT1_CHAN
NEL_GROUP3_ENA
VPDMA_INT1_CHAN
NEL_GROUP2_ENA
VPDMA_INT1_CHAN
NEL_GROUP1_ENA
VPDMA_INT1_CHAN
NEL_GROUP0_ENA
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 1-181. intc_intr1_status_ena1 Register Field Descriptions
Bit Field Type Reset Description
31-26 Reserved R 0h
25 VIP2_CHR_DS_2_UV_ER
R_INT_ENA R/W 0h
VIP2 Chroma Downsampler 2 UV Error Enabled Interrupt Status
Read indicates enabled status 0 = inactive 1 = active Writing 1 will
clear interrupt Writing 0 has no effect
24 VIP2_CHR_DS_1_UV_ER
R_INT_ENA R/W 0h
VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status
Read indicates enabled status 0 = inactive 1 = active Writing 1 will
clear interrupt Writing 0 has no effect
23 VIP1_CHR_DS_2_UV_ER
R_INT_ENA R/W 0h
VIP1 Chroma Downsampler 2 UV Error Enabled Interrupt Status
Read indicates enabled status 0 = inactive 1 = active Writing 1 will
clear interrupt Writing 0 has no effect
22 VIP1_CHR_DS_1_UV_ER
R_INT_ENA R/W 0h
VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status
Read indicates enabled status 0 = inactive 1 = active Writing 1 will
clear interrupt Writing 0 has no effect
21 NF_CHR_DS_UV_ERR_I
NT_ENA R/W 0h
Noise Filter Chroma Downsampler UV error Interrupt Enabled Status
Read indicates enabled status 0 = inactive 1 = active Writing 1 will
clear interrupt Writing 0 has no effect
20 COMP_ERR_INT_ENA R/W 0h
COMP Enabled Interrupt Status Read indicates enabled status 0 =
inactive 1 = active Writing 1 will clear interrupt Writing 0 has no
effect
19 GRPX3_INT_ENA R/W 0h
GRPX3 Enabled Interrupt Status Read indicates enabled status 0 =
inactive 1 = active Writing 1 will clear interrupt Writing 0 has no
effect
18 GRPX2_INT_ENA R/W 0h
GRPX2 Enabled Interrupt Status Read indicates enabled status 0 =
inactive 1 = active Writing 1 will clear interrupt Writing 0 has no
effect
17 GRPX1_INT_ENA R/W 0h
GRPX1 Enabled Interrupt Status Read indicates enabled status 0 =
inactive 1 = active Writing 1 will clear interrupt Writing 0 has no
effect
16 DEI_ERROR_INT_ENA R/W 0h
DEI Error Enabled Interrupt Status Read indicates enabled status 0
= inactive 1 = active Writing 1 will clear interrupt Writing 0 has no
effect