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2606B System SourceMeter® Instrument Reference Manual
Section 7: TSP command reference
2606B-901-01 Rev. B / May 2018
7-283
Usage
operationRegister
= status.operation.instrument.smu
X
.trigger_overrun.condition
operationRegister
= status.operation.instrument.smu
X
.trigger_overrun.enable
operationRegister
= status.operation.instrument.smu
X
.trigger_overrun.event
operationRegister
= status.operation.instrument.smu
X
.trigger_overrun.ntr
operationRegister
= status.operation.instrument.smu
X
.trigger_overrun.ptr
status.operation.instrument.smu
X
.trigger_overrun.enable =
operationRegister
status.operation.instrument.smu
X
.trigger_overrun.ntr =
operationRegister
status.operation.instrument.smu
X
.trigger_overrun.ptr =
operationRegister
operationRegister
The status of the operation status SMU X trigger overrun register; a zero (0)
indicates no bits set (also send 0 to clear all bits); other values indicate various bit
settings
Details
These attributes are used to read or write to the operation status SMU X trigger overrun registers.
Reading a status register returns a value. The binary equivalent of the returned value indicates which
register bits are set. The least significant bit of the binary number is bit B0, and the most significant bit
is bit B15. For example, if a value of
18
is read as the value of the condition register, the binary
equivalent is 0000 0000 0001 0010. This value indicates that bit B1 and bit B4 are set.
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
**
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*
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
* Least significant bit
** Most significant bit
For information about .condition, .enable, .event, .ntr, and .ptr registers, refer to
Enable and transition registers
(on page E-16). The individual bits of this
register are defined in the following table.
Bit
Value
Description
B0
Not used
Not applicable.
B1
status.operation.instrument.smuX.trigger_overrun.ARM
Set bit indicates that the
arm event detector of
the SMU was already in
the detected state when
a trigger was received.
Bit B1 decimal value: 2
B2
status.operation.instrument.smuX.trigger_overrun.SRC
Set bit indicates that the
source event detector of
the SMU was already in
the detected state when
a trigger was received.
Bit B2 decimal value: 4