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8. Maintenance, Checkout, and Calibration
8.10. FIM Self-Test Diagnostic Codes
R400
Experion PKS Series A Fieldbus Interface Module User's Guide
355
July 2010
Honeywell
Test Code
Target Device(s)
Failure Modes
Function
T110
ICP RAM
Destructive Pattern
Test
RAM, PLD, CPU,
buffers
Checks address and data lines by
writing a non-repeating pattern
over the whole memory, then
verifying it. Multiple patterns are
used for better coverage.
T111
ICP ASIC Register
Access Test
ICP ASIC, PLD
ASIC-RAM
interface
The hardware setup parameters
having been written to the ASIC
some time earlier, access to the
ICP ASIC registers is verified, and
the error register is verified as
zero. The ECHO_REV operation
is used to make the ASIC write its
version register to a designated
location in shared RAM. This
value is saved in RAM. The rest of
shared RAM is verified to make
sure that only the designated
location was written.
T112
ICP ASIC Unique
Address Echo Test
ICP ASIC, PLD
ASIC-RAM
interface
Correct access to the ICP shared
RAM from the ASIC is verified
through the Echo test by asking
the ASIC to write each location's
address at the address. This test
is performed once for the address
and once for the complement of
the address. Coverage is not 100
percent because only the 17 LS
address bits are supported by the
ASIC.
T113
ICP Bus Lock Test
ICP ASIC, PlD,
CPU
Verify that the ICP ASIC can be
locked out of its shared RAM by
the CPU. This is accomplished
with the ASIC Echo_REV test by :
a) Locking the bus,
b) Telling the ASIC to write a
specified address,
c) Looking at the address to see
that it did not change,
d) Unlocking the bus, and
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