GE M
EDICAL
S
YSTEMS
D
IRECTION
2380207, R
EVISION
7
LOGIQ™5 PRO S
ERVICE
M
ANUAL
5-4
Section 5-3 - Block Diagram
Figure 5-3 LOGIQ™ 5 PRO System Block Diagram (cont’d)
SIG Assy
CWDOP
Assy
(Option)
Buffer
RDS Assy
FEC Assy
OQCARD
OQCARD
OQCARD
OQCARD
Buffer
Buffer
Buffer
12 Bits ADC
FLASH
Memory
Conrtol
FPGA
12 Bits ADC
12 Bits ADC
Control
COMSO
JUSC
CONTROL
JUSC
BUS
Power
Check
HV
Control
PGC Siginal
Gen
Clock Gen. Circuit
ADDER
Harmonic Filter
SH4
for
Scan Control
Memory
Memory
PCI BUS
PCI MF for SH4
1960
for
PCI I/F
Memory
16MB
Data
Line Buffer
&
Memory
Controller
12 Bits ADC
Buffer
12 Bits ADC
JUSC
Buffer
Buffer
12 Bits ADC
Buffer
12 Bits ADC
Buffer
Voltage
Reference
12 Bits ADC
Backplane
PC2IP Board
AGP Video Card
VIC Card
Sound Card
LAN
ECC
RJ45
MOD
CDRW
EIDE
HDD
USB
USB Battery
Chipset
CPU
P4
Chipset
Main Memory
512MB
RS232
MODEM
PC BackEnd
HV Assy
ATX Power Supply
Содержание LOGIQ 5 PRO
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