SCC Asynchronous HDLC Mode and IrDA
MPC885 PowerQUICC Family Reference Manual, Rev. 2
25-4
Freescale Semiconductor
25.6
Exceptions to RFC 1549
•
An unmapped control character that follows 0x7D is modified by the XOR process. The CRC
check should catch this.
•
In addition to the abort
sequence, frames are terminated by the following errors:
— CD (carrier detect) lost
— Receiver overrun
— Framing error
— Break sequence
•
If an invalid sequence(0x7D7D) is received, the first control escape character is discarded, and the
second is unconditionally XORed with 0x20. The sequence is thus stored in the buffer as 0x5D.
25.7
Asynchronous HDLC Channel Implementation
The following points are specific to asynchronous HDLC channel implementation:
•
Flag sequence—The transmitter automatically generates the opening and closing flags. The
receiver removes opening and closing flags before writing a frame to memory and receives frames
with only one shared flag between frames, ignoring multiple flags.
•
Address field—The address field is neither generated nor examined by the microcode while
sending or receiving. The destination address field of the frame must be included in the Tx buffer.
Any address field compression, expansion, or checking must be performed by the core.
•
Control field—The control field is neither generated nor examined by the microcode during a
transfer. The control field of the frame must be included in the buffer. Any control field
compression, expansion, or checking is done by the core.
•
Frame check sequence—When sending, the frame check sequence (FCS) is appended to the frame
before the closing flag is sent. The FCS is generated on the original frame before transparency
characters, start/stop bits, or flags are added. When receiving, the FCS is checked automatically
and calculated after any transparency characters, start/stop bits, and flags are removed. For both,
the controller uses only a 16-bit CRC-CCITT polynomial.
•
Encoding—The asynchronous HDLC controller supports 8 data bits, one start bit, one stop bit, and
no parity. Program PSMR[CHLN] to 0b11 for proper operation.
•
Idle characters—When sending, the asynchronous HDLC controller sends idle characters when no
data is available; when receiving, it ignores idle characters.
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Страница 440: ...Clocks and Power Control MPC885 PowerQUICC Family Reference Manual Rev 2 14 24 Freescale Semiconductor ...
Страница 554: ...MPC885 PowerQUICC Family Reference Manual Rev 2 V 6 Freescale Semiconductor ...
Страница 606: ...SDMA Channels and IDMA Emulation MPC885 PowerQUICC Family Reference Manual Rev 2 19 20 Freescale Semiconductor ...
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Страница 780: ...SCC Ethernet Mode MPC885 PowerQUICC Family Reference Manual Rev 2 27 24 Freescale Semiconductor ...
Страница 794: ...SCC Transparent Mode MPC885 PowerQUICC Family Reference Manual Rev 2 28 14 Freescale Semiconductor ...
Страница 848: ...Serial Peripheral Interface SPI MPC885 PowerQUICC Family Reference Manual Rev 2 30 18 Freescale Semiconductor ...
Страница 882: ...Universal Serial Bus USB MPC885 PowerQUICC Family Reference Manual Rev 2 31 34 Freescale Semiconductor ...
Страница 944: ...Parallel I O Ports MPC885 PowerQUICC Family Reference Manual Rev 2 34 26 Freescale Semiconductor ...
Страница 956: ...CPM Interrupt Controller MPC885 PowerQUICC Family Reference Manual Rev 2 35 12 Freescale Semiconductor ...
Страница 1004: ...Buffer Descriptors and Connection Tables MPC885 PowerQUICC Family Reference Manual Rev 2 37 30 Freescale Semiconductor ...
Страница 1022: ...ATM Parameter RAM MPC885 PowerQUICC Family Reference Manual Rev 2 38 18 Freescale Semiconductor ...
Страница 1068: ...ATM Pace Control MPC885 PowerQUICC Family Reference Manual Rev 2 40 22 Freescale Semiconductor ...
Страница 1090: ...UTOPIA Interface MPC885 PowerQUICC Family Reference Manual Rev 2 43 8 Freescale Semiconductor ...
Страница 1120: ...AAL2 Implementation MPC885 PowerQUICC Family Reference Manual Rev 2 44 30 Freescale Semiconductor ...
Страница 1162: ...Fast Ethernet Controller FEC MPC885 PowerQUICC Family Reference Manual Rev 2 45 40 Freescale Semiconductor ...
Страница 1172: ...SEC Lite Overview MPC885 PowerQUICC Family Reference Manual Rev 2 46 8 Freescale Semiconductor ...
Страница 1176: ...SEC Lite Address Map MPC885 PowerQUICC Family Reference Manual Rev 2 47 4 Freescale Semiconductor ...
Страница 1214: ...SEC Lite Execution Units MPC885 PowerQUICC Family Reference Manual Rev 2 48 38 Freescale Semiconductor ...
Страница 1312: ...Byte Ordering MPC885 PowerQUICC Family Reference Manual Rev 2 A 8 Freescale Semiconductor ...
Страница 1313: ...MPC885 PowerQUICC Family Reference Manual Rev 2 Freescale Semiconductor B 1 Appendix B Serial Communications Performance TBD ...
Страница 1314: ...Serial Communications Performance MPC885 PowerQUICC Family Reference Manual Rev 2 B 2 Freescale Semiconductor ...
Страница 1320: ...Register Quick Reference Guide MPC885 PowerQUICC Family Reference Manual Rev 2 C 6 Freescale Semiconductor ...
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Страница 1370: ...MPC880 MPC885 PowerQUICC Family Reference Manual Rev 2 E 4 Freescale Semiconductor ...
Страница 1384: ...Serial ATM Scrambling Reception and SI Programming MPC885 PowerQUICC Family Reference Manual Rev 2 H 6 Freescale Semiconductor ...
Страница 1386: ...Revision History MPC885 PowerQUICC Family Reference Manual Rev 2 I 2 Freescale Semiconductor ...