Freescale Semiconductor PowerQUICC MPC870, Справочное руководство

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External Bus Interface
MPC885 PowerQUICC Family Reference Manual, Rev. 2
13-14 Freescale Semiconductor
13.4.3 Burst Transfers
The MPC885 or other synchronous external bus devices use burst transfers to access 16-byte operands. A
burst accesses a 16-byte block aligned to a 16-byte memory boundary by supplying a starting address that
points to one of the words and requiring the memory device to sequentially drive/sample each word on the
data bus. The selected slave device must internally increment A28 and A29 (and A30 in the case of a 16-bit
port size slave device) of the supplied address for each transfer, causing the address to wrap around at the
end of the four-word block. For slaves controlled by the memory controller, the MPC885 increments the
address on A[28:31] or BADDR[28:30].
Address and transfer attributes supplied by the master bus remain stable during the transfers; the selected
device terminates each transfer by asserting TA after each word transferred on the data bus. The MPC885
also supports burst-inhibited transfers for slave devices that do not support bursting. For this type of cycle,
the selected slave device supplies/samples the address of the first word of the burst and asserts the
burst-inhibit signal (BI) with TA for the first transfer of the burst access. The MPC885 responds by
terminating the burst and accessing the rest of the 16-byte block, using three read/write cycles (each one
for a word) for a 32-bit port-width slave, seven read/write cycles for a 16-bit port-width slave, or fifteen
read/write cycles for a 8-bit port-width slave.
The general case of burst transfers assumes that external memory has a 32-bit port size. The MPC885
provides an effective mechanism for interfacing with 16-bit port size memories and 8-bit port size
memories allowing burst transfers to these devices when they are controlled by the internal memory
controller. In this case, the MPC885 attempts to initiate a burst transfer as in the normal case. If, in a cycle
before the TA is asserted for the first beat, the memory controller responds that the port size is 16-/8-bits
and that the burst is accepted, the MPC885 completes a 8-/16-beat burst. Each data beat effectively
transfers only 2/1 bytes. Note that this 8-/16-beat burst is considered an atomic transaction, so the MPC885
does not allow other unrelated master accesses or bus arbitration between transfers.
13.4.4 Burst Operations
The MPC885 burst mechanism uses additional signals to the basic protocol: BURST indicates that the
cycle is a burst cycle, burst data in progress (BDIP) indicates the duration of the burst data, and burst
inhibit (BI) indicates whether the slave supports bursts. Along with asserting TS, the master drives the
address, address attributes, and BURST signals to indicate that a burst transfer is being initiated. Slaves
that support bursting negate BI. If the slave cannot burst, it asserts BI. During the data phase of a burst
write cycle the master drives the data. The master also asserts BDIP if it intends to drive the data beat after
the current one.
When the slave has received the data, it asserts TA to indicate to the master that it is ready for the next
transfer. The master again drives the next data and asserts or negates BDIP. If the master does not intend
to drive another data beat, it negates BDIP to indicate to the slave that the next data beat is the last one in
the burst write.
Bursts performed by MPC885 internal masters are always 16 bytes. The MPC885 memory controller
responds only to fixed-length bursts (also typically programmed to be 16 bytes). Therefore, devices in an
MPC885 system should attempt only 16-byte burst transfers except for external masters with a dedicated
chip select, such as an external MPC603 that bursts to a chip select programmed for a 32-byte burst.