ATM Parameter RAM
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor
38-15
38.7
Multi-PHY State Register (MPHYST) (UTOPIA Master Only)
The APC multi-PHY state register (MPHYST), shown in
Figure 38-8
, contains state and control
parameters for ESAR multi-PHY UTOPIA operation.
5–7
NMPHY
Reserved in ESAR mode.
(Classic SAR only) Number of (multiple) PHYs. Valid only for the SCC4 parameter RAM when in
UTOPIA multi-PHY mode; in all other parameter RAM pages (SCC1–3), this field should be
cleared. NMPHY specifies the total number of PHY devices connected to the UTOPIA port.
000 1 PHY
001 2 PHYs
010 3 PHYs
011 4 PHYs
1xx Reserved
8–10
CMPHY
Reserved in ESAR mode.
(Classic SAR only) Current multi-PHY. Valid only for the SCC4 parameter RAM when in UTOPIA
multi-PHY mode. CMPHY is used only by the CP and should be initialized with the same value
programmed in NMPHY.
11
—
Reserved
12
ESAR
Enhanced SAR support. This bit should be set when initializing ESAR operation. In ESAR mode,
NMPHY and CMPHY are defined by the MPHYST and the APC also extends to support this
multi-PHY master
configuration. This bit should be cleared if classic SAR operation is required.
0 ESAR APC functions are disabled.
1 ESAR APC functions APC and MPHY are enabled.
13
DIS
APC disabled status flag. Valid for serial ATM only. Set by the transmitter when a global FIFO
underrun (GUN) exception occurs. Should be cleared during initialization.
14
PL2
Reserved in ESAR mode.
Priority level 2—classic SAR only. Enables the second APC priority level. Applies only when
programming for classic SAR compatibility. Note that when in ESAR mode, PL2 is reserved and
should be cleared.
0 Disable the second-level APC scheduling table.
1 Enable the second-level APC scheduling table.
15
MPY
Enable multi-PHY mode. Valid only for the SCC4 parameter RAM when in UTOPIA mode. Applies
only when programming for classic SAR compatibility. For additional information about the
multi-PHY configuration, see
Section 39.6, “Multi-PHY (MPHY) Configuration.”
0 Single PHY mode
1 Multiple PHY mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
—
NMPHY
—
CMPHY
—
Reset
—
Oper R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addr
0x90 in SCC4 parameter RAM
Figure 38-8. MPHY State Register (MPHYST)
Table 38-13. APCST Field Descriptions (continued)
Bit(s)
Name
Description
Содержание PowerQUICC MPC870
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