Freescale Semiconductor PowerQUICC MPC870, Справочное руководство

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System Development and Debugging
MPC885 PowerQUICC Family Reference Manual, Rev. 2
53-26 Freescale Semiconductor
supplies signals to the core. The trap enable bits, VSYNC bit, and the breakpoint bits of this register are
loaded from the development port shift register as the result of trap enable mode transmissions. The trap
enable bits are reflected in ICTRL and LCTRL2.
Section 53.5.1.1, “Comparator A–H Value Registers
(CMPA–CMPH),” describes support registers.
53.3.2.2.3 Development Port Registers Decode
The development port shift register is selected when the core accesses DPIR or DPDR. Accesses to either
register occur in debug mode and appears on the internal bus as an address and the assertion of an address
attribute signal indicating that an SPR is being accessed. In debug mode, the core reads the DPIR to fetch
all instructions; it reads and writes to the DPDR to transfer data between the core and external development
tools. DPIR and DPDR are pseudo-registers; decoding either causes the development port shift register to
be accessed. Debug mode logic knows whether the core is fetching instructions or reading or writing data.
A sequence error is signaled to the external development tool when the core expected result and the GPR
results do not match, for example if an instruction is received when data is expected.
53.3.2.3 Development Port Serial Communications–Clock Mode
All development port serial transmissions are synchronous communications. The development port
supports two ways to clock serial transmissions.
53.3.2.3.1 Asynchronous Clocked Mode—Using DSCK
The first clock mode is called asynchronous clocked since the input clock DSCK is asynchronous with
CLKOUT. To ensure that data on DSDI is sampled correctly, transitions on DSDI must meet all setup and
hold times with respect to the rising edge of DSCK. This clock mode allows communications with the port
from a development tool which does not have access to CLKOUT or where CLKOUT has been delayed
or skewed.
Figure 53-9 shows the serial communications asynchronous clocked timing.
Figure 53-9. Asynchronous Clocked Serial Communications
DSCK
DSDI MODE CNTRL DI<0>
S<0> S<1> DO<0>
START
READY DSDO
Debug port drives the “ready” bit onto DSDO when ready for a new transmission.
NOTE: DSCK and DSDI transitions are not required to be synchronous with CLKOUT.
DI<N-2> DI<N-1> DI<N>
DO<N-2>DO<N-1> DO<N>
Debug Port detects the “start” bit on DSDI and follows the
“ready” bit with two status bits and 7 or 32 output data bits.
Development Tool drives the “start” bit on DSDI (after detecting the “ready” bit
on DSDO when in debug mode). The “start” bit is immediately followed by a
mode bit and a control bit and then 7 or 32 input data bits.