Freescale Semiconductor PowerQUICC MPC870, Справочное руководство

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Instruction and Data Caches
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 7-23
MD_CTR[CIDEF]; and the entire memory space defaults to the guarded attribute. See Chapter 8,
“Memory Management Unit,” for more information.
A data cache access begins with a load or store request from the load/store unit (LSU) in the core. The data
cache has a 32-bit data path to and from the load/store unit, allowing for a 4-byte transfer per cycle. As
shown in
Figure 7-2 , bits 20–27 of the data address provide the index to select a set (0–255) within the data
cache array. The tags from both ways of the set are compared against bits 0–19 of the data address. If a
match is found and the matched entry is valid, it is a cache hit. If neither tag matches or the matched tag
is not valid, it is a cache miss.
The data cache operates in both write-through and write-back modes as programmed by the memory/cache
access attributes. These modes affect store hit and store miss behavior of the data cache. Load hits and load
misses behave the same regardless of the write-through/write-back mode. If two logical blocks map to the
same physical block, it is considered a programming error for them to specify different cache write
policies.
Each data cache block contains two state bits that implement a three-state
(modified-valid/unmodified-valid/invalid) protocol. The MPC885 does not support snooping of the data
cache. All memory is considered to have memory coherency not required attributes. Therefore, software
must maintain data cache coherency. The MPC885 does not provide support for snooping external bus
activity. All coherency between the internal caches and external agents (memory or I/O devices) must be
controlled by software. In addition, there is no mechanism provided for DMA or other internal masters to
access the data cache directly.
The MPC885 data cache includes the following operational features:
• Single-cycle cache access on hit and one clock latency added for miss
• The data cache supports hits under load misses.
• 1-word store buffer
• Store misses bypass the data cache (no-allocate store miss) in write-through mode
• 4-word copyback buffer holds replaced modified cache blocks until they can be written to memory
• Cache operation is blocked until the cache block is written to the cache array for store misses in
write-back mode,
• The data cache supports the sync instruction through a cache pipe clean indication to the core.
7.6.1 Data Cache Load Hit
In the case of a data cache load hit, the requested word is transferred to the load/store unit. The LRU state
of the set is updated, but the state bits remain unchanged.The access time for a data cache load hit is one
clock cycle (that is, zero wait states).
7.6.2 Data Cache Read Miss
In the case of a data cache load miss, a block in the cache array is selected to receive the data from memory.
The selection algorithm gives first priority to invalid blocks. If both blocks in the set are marked invalid,
the block in way 0 is selected. If neither of the two blocks in the selected set are invalid, the least recently