Freescale Semiconductor PowerQUICC MPC870, Справочное руководство

Страница: 640 / 1426

Serial Interface
MPC885 PowerQUICC Family Reference Manual, Rev. 2
20-34 Freescale Semiconductor
3. SICR = 0x00C0_4000. SCC2 and SCC3 are connected to the TSA. SCC3 supports the grant
mechanism since it is on the D channel.
4. PAODR[9] = 1. Configure L1TXDa to be an open-drain output.
5. PAPAR[7–9] = 0b111. Configure L1TXDa, L1RXDa, and L1RCLKa.
6. PADIR[7–9] = 0b011. Configure L1TXDa, L1RXDa, and L1RCLKa.
7. If the 1
×
GCI data clock is required, configure L1CLKOa as an output by setting PBPAR[20] and
PBDIR[20].
8. PCPAR[4] = 1. Configure L1RSYNCa.
9. SIGMR = 0x04. Enable TDMa (one static TDM).
10. SICMR is not used.
11. SISTR and SIRP do not need to be read but can be used for debugging when channels are enabled.
12. Enable SCC3 for HDLC operation (to handle the LAPD protocol of the D channel), configure
SCC2 and SMC2 as needed and enable SMC1 for SCIT operation.
20.3 NMSI Configuration
The SI supports a non-multiplexed serial interface (NMSI) mode for the SCCs and SMCs. The decision of
whether to connect the SCCs to the NMSI is made in the SICR; the SMCs are connected through SIMODE.
An SCC or SMC can be connected to the NMSI, regardless of the other channels connected to a TDM
channel. However, NMSI pins can be multiplexed with other functions at the parallel I/O lines. Therefore,
if a combination of TDM and NMSI channels are used, the decision of which SCC and SMC to connect
and where to connect them should be made by consulting the pinout in
Chapter 2, “Memory Map.”
The clocks that are provided to the SCCs and SMCs are derived from four internal baud rate generators
and eight external CLK pins. There are two main advantages to this bank-of-clocks approach. First, an
SCC or SMC is not forced to choose its clock from a predefined pin or baud rate generator. Second, if a
group of receivers and transmitters need the same clock rate they can share the same pin, leaving other pins
available other functions and minimizing the potential skew between multiple clock sources.
The baud rate generators also make their clocks available to external logic, regardless of whether the BRGs
are being used by an SCC or an SMC. The BRGOn pins are multiplexed with other functions, so all
BRGOn pins may not always be available. See
Chapter 2, “Memory Map.”
The following restrictions apply to the bank-of-clocks mapping:
• Only eight of the twelve clock sources can be connected to a given SCC receiver or transmitter.
• The SMC transmitter must have the same clock source as the receiver when connected to
the NMSI.
Once the clock source is selected, the clock is given an internal name. For the SCCs, the name is RCLKx
and TCLKx and for the SMCs, the name is simply SMCLKx. These internal names are used only in NMSI
mode to specify the clock that is sent to the SCC or SMC. These names do not correspond to physical pins
on the MPC885. Note the internal RCLKx and TCLKx can be used as inputs to the DPLL unit, which is
inside the SCCx; thus, RCLKx and TCLKx are not always required to reflect the actual bit rate on the line.