Freescale Semiconductor PowerQUICC MPC870, Справочное руководство

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UTOPIA Interface
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 43-3
4–7 REHS Receive expanded header size. Program REHS to match ECSIZE in the parameter RAM.
This field is reserved when REC is cleared.
0
1 byte expanded header.
1 2 byte expanded header
.
.
.
11 12 byte
12-14 Not used
15
0
8–12 MPHY Multi PHY number. This field is common to Rx and Tx. In master mode, MPHY defines the number
of PHYs on the UTOPIA bus by defining the last PHY number used. In slave mode, MPHY defines
the PHY ID of this UTOPIA slave port. In combined master/slave mode, MPHY defines both; that is,
the slave ID has to be the “last” PHY in the multi-PHY system. Unused bits (when ADDPIN
π
0b11)
should be cleared.
Note: 0x1f, i.e., 31 is a reserved value.
13 RMPYE Receive multi-PHY enable.
0 Receiver is operating in single-PHY mode (according to UTOPIA level1).
1 Receiver is operating in multi-PHY mode (according to UTOPIA level 2, PHY polling method)
14 RMPYP
/RSPY
B
RMPYP—applies to multi-PHY master operation only. Receive multi-PHY priority.
0 Round robin priority. All PHYs are given equal priority in a circular polling method. (Polling always
starts with the next consecutive PHY number.)
1 Fixed priority. PHY0 is given the highest priority; the “last” PHY has the lowest priority. (Polling
always starts with PHY0. If PHY0 does not need attention, polling proceeds to PHY1, and so on
to the last PHY.)
RSPYB—applies to single-PHY operation only. Receive single-PHY back-to-back cells.
0 Disable back-to-back cell reception.
1 Enable back-to-back cell reception.
15 RHECI Receive HEC byte insertion in expanded cell mode (REC =1).
0 No HEC insertion in expanded cell.
1 HEC insertion. The cell HEC is read from the UTOPIA interface and then dumped by the receiver.
16 TSL Transmit UTOPIA slave mode. Valid in split bus mode only (SPLIT=1). Selects master or slave
operation for the transmitter. See
Table 43-2 for the active signal names from the master’s point of
view. Note that when TSL is set (slave operation), the transmitter is driving the master’s receive
signals.
0 The transmit UTOPIA split bus is operating as master (ATM side).
1 The transmit UTOPIA split bus is operating as slave (PHY side).
17 TCLK Transmit (main) UTOPIA clock selector. The UTOPIA clocks can be either generated internally using
the system clock or supplied by an external clock.
0 UTOPIA clock is internal. See
Section 42.2.1, “System Clock Control Register (SCCR).” UtpClk
is an output.
1 UTOPIA clock is external. UtpClk is an input.
18 TEC Transmit expanded cell. Program TEC to match STSTATE[EC] in the parameter RAM.
0 Standard 53-byte ATM cell is used.
1 Expanded cell method is used on all UTOPIA cells. Cell length can be 52 to 65 bytes, as defined
by the TEHS and THECI fields.
Table 43-1. UTMODE Field Descriptions (continued)
Bit Name Description