Freescale Semiconductor PowerQUICC MPC870, Справочное руководство

Страница: 645 / 1426

Serial Interface
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 20-39
20.4.2 Autobaud Operation on the SCC UART
During the autobaud process, the SCC UART deduces the baud rate of its received character stream by
examining the received pattern and its timing. A built-in autobaud control function automatically measures
the length of a start bit and modifies the baud rate accordingly.
If the autobaud bit BRGCn[ATB] is set, the autobaud control function starts searching for a low level on
the corresponding RXDn input, which it assumes marks the beginning of a start bit, and begins counting
the start bit length. During this time, the BRG output clock toggles for 16 BRG clock cycles at the BRG
source clock rate and then stops with BRGOn in the low state.
When RXDn goes high again, the autobaud control block rewrites BRGCn[CD, DIV16] to the divide ratio
found, which at high baud rates may not be exactly the final rate desired (for example, 56,600 may result
rather than 57,600). An interrupt can be enabled in the UART SCC event register to report that the
autobaud controller rewrote BRGCn. The interrupt handler can then adjust BRGCn[CD, DIV16] (see
Table 20-14 ) for accuracy before the first character is fully received, ensuring that the UART recognizes
all characters.
After a full character is received, the software can verify that the character matches a predefined value
(such as ‘a’ or ‘A’). Software should then check for other characters (such as ‘t’ or ‘T’) and program the
preferred parity mode in the UART’s protocol-specific mode register (PSMR).
Note that the SCC associated with this BRG must be programmed to UART mode and select the 16
×
option for TDCR and RDCR in the general SCC mode register (GSMR_L). Input frequencies such as
1.8432, 3.68, 7.36, and 14.72 MHz should be used. The SCC performing the autobaud function must be
connected to that SCC’s autobaud BRG; that is, SCC2 must be clocked by BRG2, and so on.
Also, to detect an autobaud lock and generate an interrupt, the SCC must receive three full Rx clocks from
the BRG before the autobaud process begins. To do this, first clear BRGC[ATB] and enable the BRG
receive clock to the highest frequency. Then, immediately before the autobaud process starts (after device
initialization), set BRGCn[ATB].
19–30 CD Clock divider. CD presets an internal 12-bit counter that is decremented at the DIV16 output rate.
When the counter reaches zero, it is reloaded with CD. CD = 0xFFF produces the minimum clock
rate for BGRO (divide by 4,096); CD = 0x000 produces the maximum rate (divide by 1). When
dividing by an odd number, the counter ensures a 50% duty-cycle by asserting the terminal count
once on clock low and next on clock high. The terminal count signals counter expiration and toggles
the clock. See
Section 20.4.3, “UART Baud Rate Examples.”
31 DIV16 Divide-by-16. Selects a divide-by-1 or divide-by-16 prescaler before reaching the clock divider. See
Section 20.4.3, “UART Baud Rate Examples.”
0 Divide by 1
1 Divide by 16
Table 20-13. BRGC n Field Descriptions (continued)
Bits Name Description