Freescale Semiconductor PowerQUICC MPC870, Справочное руководство

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Instruction and Data Caches
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 7-25
7.6.4 Write-Back Mode
In write-back mode, store operations do not necessarily update external memory. Data is only copied to
external memory when a copyback operation is required (or the cache is deliberately flushed). For this
reason the write-back mode is the preferred mode of operation when it is necessary to minimize external
bus utilization and as a side effect, reduce operational power consumption.
7.6.4.1 Data Cache Store Hit in Write-Back Mode
In the case of a data cache store hit in write-back mode, the cache operation depends on the state bits of
the cache block. If the store hit is to a modified-valid cache block, data is stored in the cache block and the
block stays marked modified-valid. If the store hit is to a unmodified-valid cache block, data is stored in
the cache block and the block is marked modified-valid. In either case, the LRU state of the set is updated
to reflect the hit.
7.6.4.2 Data Cache Store Miss in Write-Back Mode
In the case of a data cache store miss in write-back mode, the data cache must establish the block in the
cache array before modifying that block. Therefore, a block in the cache array is selected to receive the
data from memory and from the load/store unit. The selection algorithm gives first priority to invalid
blocks. If both blocks in the set are marked invalid, the block in way 0 is selected. If neither of the two
blocks in the selected set are invalid, the least recently used block is selected for replacement. If the
replacement block is marked modified-valid, it is temporarily stored in the copyback buffer to be written
to memory later. Locked cache blocks are never replaced.
After a cache block has been selected, the word-aligned physical address of the store data is sent to the SIU
with a 4-word burst transfer read request. The SIU arbitrates for the bus and initiates a burst read. The
transfer begins with the aligned word containing the requested data (critical word first), followed by the
remaining words of the cache block (if any), then by any remaining words at the beginning of the block
(wrap-around). As the critical word is received from the internal bus, it is merged in the burst buffer with
the store data from the load/store unit. If no bus errors are encountered during the burst buffer fill
operation, the cache block is written into the cache array and marked modified-valid. The data cache does
not support further requests until the entire block is written to the cache array. If the machine has stalled
waiting for the store to complete, execution is allowed to resume when the cache block is written into the
cache array.
If a bus error is encountered while loading the target data cache block, even on a word not accessed by the
load/store unit, the cache block is not modified, and a machine check exception is generated.
After the cache block with the requested data has been loaded from memory, the cache block in the
copyback buffer is sent to the SIU to be written to memory. The data cache can support further requests,
as long as they hit in the cache, while performing the copyback to memory. If a bus error is encountered
during the copyback, a machine check exception is generated (the copyback error is an imprecise
exception). The address and data in the copyback buffer can be read as specified in
Section 7.3.2.1,
“Reading Data Cache Tags and Copyback Buffer.”