Freescale Semiconductor PowerQUICC MPC870, Справочное руководство

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External Bus Interface
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 13-25
Table 13-2 lists the bytes required on the data bus for read cycles.
Table 13-3 lists data transfer patterns for write cycles when the MPC885 initiates accesses.
13.4.6 Arbitration Phase
The external bus design provides for a single bus master at any one time, either the MPC885 or an external
device. The arbitration of external bus devices contending for bus mastership may be handled either by an
external central bus arbiter or by the internal on-chip arbiter. In the latter case, the system is optimized for
one external bus master besides the MPC885. The arbitration configuration (external or internal) is set at
system reset. See
Section 15.8, “External Master Support.”
Each bus master must have bus request (BR), bus grant (BG), and bus busy (BB) signals. A device needing
the bus asserts BR and waits for the arbiter to assert BG. The new master must look at BB to ensure that
no other master is driving the bus before it can assert BB to assume bus mastership. (Note that the internal
Table 13-2. Data Bus Requirements for Read Cycles
Transfer
Size
TSIZ[0:1]
Address 32-Bit Port
1
1
Denotes a byte not required during that read cycle.
16-Bit Port
1
8-Bit Port
A30 A31 D[0:7] D[8:15] D[16:D3] D[24:31] D[0:7] D[8:15] D[0:7]
Byte 0 1 0 0 OP0 — — — OP0 — OP0
0 1 — OP1 — — — OP1 OP1
1 0 — — OP2 — OP2 — OP2
1 1 — — — OP3 — OP3 OP3
Half-Word 1 0 0 0 OP0 OP1 — — OP0 OP1 OP0
1 0 — — OP2 OP3 OP2 OP3 OP2
Word 0 0 0 0 OP0 OP1 OP2 OP3 OP0 OP1 OP0
Table 13-3. Data Bus Contents for Write Cycles
Transfer
Size
TSIZ[0:1]
Address External Data Bus Pattern
1
1
Denotes a byte not required during that read cycle.
A30 A31 D[0:7] D[8:15] D[16:D3] D[24:31]
Byte 0 1 0 0 OP0 — — —
0 1 OP1 OP1 — —
1 0 OP2 — OP2 —
1 1 OP3 OP3 — OP3
Half-Word 1 0 0 0 OP0 OP1 — —
1 0 OP2 OP3 OP2 OP3
Word 0 0 0 0 OP0 OP1 OP2 OP3