Freescale Semiconductor PowerQUICC MPC870, Справочное руководство

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Serial Communications Controllers
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 21-13
descriptor’s R bit to be set before proceeding. Thus, the CP does no look-ahead descriptor processing and
does not skip BDs that are not ready. When the CP sees a BD’s W bit (wrap) set, it returns to the start of
the BD table after this last BD of the table is processed. The CP clears R (not ready) after using a TxBD,
which keeps it from being retransmitted before it is confirmed by the core. However, some protocols
support a continuous mode (CM), for which R is not cleared (always ready).
The CP uses RxBDs similarly. When data arrives, the CP performs required processing on the data and
moves resultant data to the buffer pointed to by the first BD; it continues until the buffer is full or an event,
such as an error or end-of-frame detection, occurs. The buffer is then closed; subsequent data uses the next
BD. If E = 0, the current buffer is not empty and it reports a busy error. The CP does not move from the
current BD until E is set by the core (the buffer is empty). After using a descriptor, the CP clears E (not
empty) and does not reuse a BD until it has been processed by the core. However, in continuous mode
(CM), E remains set. When the CP discovers a descriptor’s W bit set (indicating it is the last BD in the
circular BD table), it returns to the beginning of the table when it is time to move to the next buffer.
21.4 SCC Parameter RAM
Each SCC parameter RAM area begins at the same offset from each SCC base area. The protocol-specific
portions of the SCC parameter RAM are discussed in the specific protocol descriptions and the part that is
common to all SCC protocols is shown in
Table 21-5 .
Some parameter RAM values must be initialized before the SCC can be enabled. Other values are
initialized or written by the CP. Once initialized, most parameter RAM values do not need to be accessed
because most activity centers around the descriptors rather than the parameter RAM. However, if the
parameter RAM is accessed, note the following:
• Parameter RAM can be read at any time.
• Tx parameter RAM can be written only when the transmitter is disabled—after a
STOP TRANSMIT
command and before a
RESTART TRANSMIT
command or after the buffer/frame finishes
transmitting after a
GRACEFUL STOP TRANSMIT
command and before a
RESTART TRANSMIT
command.
• Rx parameter RAM can be written only when the receiver is disabled. Note the
CLOSE RX BD
command does not stop reception, but it does allow the user to extract data from a partially full Rx
buffer.
• See Section 21.4.7, “Reconfiguring the SCCs.”
Table 21-5 shows the parameter RAM map for all SCC protocols. Boldfaced entries must be initialized by
the user.
Table 21-5. SCC Parameter RAM Map for All Protocols
Offset
1
Name Width Description
0x00 RBASE Hword Rx/TxBD table base address—offset from the beginning of dual-port RAM. The BD
tables can be placed in any unused portion of the dual-port RAM.
Values in RBASE and TBASE should be multiples of eight.
0x02 TBASE Hword
0x04 RFCR Byte Rx function code. See Section 21.4.1, “Function Code Registers (RFCR and TFCR).”
0x05 TFCR Byte Tx function code. See Section 21.4.1, “Function Code Registers (RFCR and TFCR).”