Freescale Semiconductor PowerQUICC MPC870, Справочное руководство

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MPC885 Instruction Set
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 5-19
5.2.5.2.1 eieio Behavior
The purpose of eieio is to prevent loads and stores from executing speculatively when appropriate. This
might be desirable for a FIFO, where performing a read or write changes the FIFO's data. This should not
be done unless it is certain that the instruction will be completed and not cancelled.
The same function as eieio can be accomplished by defining a memory space as having the guarded
attribute in the MMU, in which case, the eieio instruction is redundant.
However, eieio could be useful in the rare event that a region where speculative accesses are not allowed
lies in the middle of a non-guarded page.
5.2.5.2.2 isync Behavior
The isync instruction is context synchronizing, which guarantees that all of the effects of previous
instructions are in place and any instructions in the instruction queue are flushed (which means all
instructions that were in the instruction queue need to be refetched). In the MPC885, fetching an isync
instruction causes fetch to stall, so no refetching is required. On the MPC885, writes to SPRs and MSR
that affect context are automatically context synchronizing; thus, an isync is not required before these
instructions. However, isync should be inserted after these instructions to ensure that instructions are
fetched in the appropriate context. Furthermore, load/store instructions that update the MMU page tables
in external memory should both be preceded and followed by an isync to ensure that instructions before
and after such instructions are fetched and completed in the appropriate context.
5.2.5.3 Memory Control Instructions—VEA
Memory control instructions include the following types:
• Cache management instructions
• Translation lookaside buffer (TLB) management instructions
This section describes the user-level cache management instructions defined by the VEA. See
Section 5.2.6.3, “Memory Control Instructions—OEA,” for information about supervisor-level cache and
translation look aside buffer management instructions.
The instructions listed in Table 5-19 provide user-level programs the ability to manage on-chip caches.
As with other memory-related instructions, the effect of the cache management instructions on memory
are weakly ordered. If the programmer needs to ensure that cache or other instructions have been
performed with respect to all other processors and system mechanisms, a sync instruction must be placed
in the program following those instructions.
Table 5-18. Memory Synchronization Instructions—VEA
Name Mnemonic Syntax MPC885 Notes
Enforce In-Order
Execution of I/O eieio — During execution, the LSU waits for previous accesses to terminate before
beginning accesses associated with load/store instructions after an
eieio .
Instruction
Synchronize isync — The isync instruction waits for all previous instructions to complete and
discards any prefetched instructions, causing subsequent instructions to be
refetched from memory.