Freescale Semiconductor PowerQUICC MPC870, Справочное руководство

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MPC885 Overview
MPC885 PowerQUICC Family Reference Manual, Rev. 2
1-16 Freescale Semiconductor
The IU uses thirty-two 32-bit GPRs for source and target operands. Typically, it can execute one integer
instruction each clock cycle. Each element in the integer block is clocked only when valid data is in the
data queue and is ready for operation. This holds power consumption of the device to the absolute
minimum.
The core is integrated with MMUs as well as instruction and data caches. Each MMU provides a 32-entry,
fully-associative instruction and data TLB, with multiple page sizes of 4, 16, 512, and 256 Kbytes and
8 Mbytes. It supports 16 virtual address spaces with 8 protection groups. Three special scratch registers
support software table search and update operations.
The instruction cache is two-way, set associative with physical addressing. It allows single-cycle access
on hits with no added latency for misses. It has four words per block, supporting a four-beat burst line fill
using an LRU (least recently used) replacement algorithm. The cache can be locked on a per-cache-block
basis for application-critical routines.
The data cache is two-way, set associative with physical addressing. It allows single-cycle accesses on hits
with one added clock latency for misses. It has four words per cache block, supporting burst line fill using
LRU replacement. The cache can be locked on a per-block basis for application critical routines. The data
cache can be programmed through the MMU to support copy-back or write-through. Cache-inhibit mode
can be programmed per MMU page.
The debug interface provides debug capabilities without degrading operation speed. This interface
supports six watchpoint pins that detect software events. Four of its eight internal comparators operate on
the effective address on the address bus, two operate on the effective address on the data address bus, and
two operate on the data bus. The core can make comparisons, using operators =,
≠
, <, and >, to generate
watchpoints. Each watchpoint can then generate a breakpoint that can be configured to trigger in a
programmable number of events.
1.3 System Interface Unit (SIU)
The SIU on the MPC885 family integrates general-purpose features useful in almost any 32-bit processor
system. Dynamic bus sizing allows 8-, 16-, and 32-bit peripherals and memory to exist in the 32-bit system
bus mode.
The SIU also provides power management functions, reset control, decrementer, and timebase.
The memory controller supports up to eight memory banks with glueless interfaces to DRAM, SRAM,
SSRAM, EPROM, Flash EPROM, SDRAM, EDO, and other peripherals with 2-clock-cycle access to
external SRAM and bursting support. It provides variable block sizes from 32 Kbytes to 256 Mbytes. The
memory controller provides 0–30 wait states for each memory bank and can use address type matching to
qualify each memory bank access. It provides four byte-enable signals, an output-enable signal, and a boot
chip select available at reset.
The DRAM interface supports port sizes of 8, 16, and 32 bits. Memory banks can be defined in depths of
256 or 512 Kbytes or 1, 2, 4, 8, 16, 32, or 64 Mbytes for all port sizes. The memory depth can be 64 and
128 Kbytes for 8-bit memory or 128 and 256 Mbytes for 32-bit memory. The DRAM controller supports
page-mode access for successive transfers within bursts. The MPC885 supports a glueless interface to one
bank of DRAM, while external buffers are required for additional memory banks. The refresh unit
provides CAS before RAS, a programmable refresh timer, refresh active during external reset, disable