Freescale Semiconductor PowerQUICC MPC870, Справочное руководство

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ATM Overview
MPC885 PowerQUICC Family Reference Manual, Rev. 2
36-10 Freescale Semiconductor
RAM, or an external content-addressable memory (CAM). If the header has no match the incoming cell is
treated as an AAL0 cell, and is passed to the global raw cell queue (channel 0). If the cell is matched to a
channel the channel status is read from the receive connection table (RCT). As the FIFO of the SCC fills,
the received cell is read from the FIFO, the HEC is checked, and the cell is optionally descrambled. Cells
with HEC errors are passed to the global raw cell queue, and the HEC error is recorded in the BD. The
receiver screens out idle cells.
After each cell is assembled, either the entire cell (for AAL0 connections) or the cell payload (for AAL5
connections) is copied to external memory, and the RCT is updated. If no empty buffer is available for the
received channel in the BD table, an interrupt is generated and the cell is discarded.
CRC32 is checked on the cell payload for AAL5 connections, with pass/fail indication provided in the last
BD of the received CPCS_PDU. The end of an AAL5 frame is indicated by the PTI[1] bit in the received
cell header. When this end-of-frame indication occurs, the receiver separates the trailer of the CPCS-PDU
from the user data. The length field is compared against the length calculated during the frame receive
operation, the pads are removed as required, the CPCS-UU and CPI are copied to the BD, and the receive
buffer is closed. An interrupt can be optionally generated to declare the end of a receive frame. Detected
CRC or length errors are marked in the BD and an interrupt can be generated.
When AAL0 cells are received the ATM controller copies the cell (except the HEC) from the SCC FIFO
to the next receive buffer in the channel’s BD table. The ATM controller calculates and optionally checks
CRC10 on the cell payload. This option supports the OAM cell check per ITU specification I.610.
36.7.2.1 Cell Delineation
In serial mode cell delineation is part of the receiver flow control. The ATM controller provides SDH/PDH
oriented cell delineation on an octet basis using the HEC mechanism defined in the ITU specification
I.432. The MPC885 can perform bit-aligned cell delineation by searching the bit stream to find the cell
alignment point without an octet-align synchronization signal.
When cell reception begins, the ATM controller attempts to acquire the correct cell delineation. Once
locked onto the cell boundaries of the incoming data stream, the ATM controller remains synchronized
unless excessive errors disrupt the flow. A status bit (ASTATUS[LOCK]) indicates the current delineation
status, and an interrupt (SCCE[SYNC]) can be generated whenever the cell lock status changes. Cells
received before proper cell delineation is achieved are stored in the global raw cell queue.
36.7.3 Cell Payload Scrambling/Descrambling
Cell payload scrambling and descrambling can be performed in the cell stream using the X
43
+1 scrambling
algorithm. The ATM controller automatically transmits an empty cell following initialization to establish
the 43-bit delay line and thereby avoid data corruption. On cell reception, the descrambling algorithm
self-synchronizes before the HEC delineation process is complete and valid cell reception begins.
36.8 ATM Pace Control (APC)
The ATM pace controller determines the next channel (or n channels) to be transmitted and writes the
channel number of these channels in the transmit queue every APC slot time. The transmitter sends one
cell for each channel entry in the transmit queue.