Fast Ethernet Controller (FEC)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
45-38
Freescale Semiconductor
Table 45-36. Transmit Buffer Descriptor (TxBD) Field Descriptions
Bits
Name
Description
0
R
Ready, written by FEC and user
0 The buffer associated with this BD is not ready for transmission. The user can manipulate
this BD or its associated buffer. The FEC clears R after the buffer is sent or an error occurs.
1 The user-prepared buffer has not been sent or is being sent. The user cannot update the
BD while R = 1.
1
TO1
Transmit software ownership bit. This field is available for use by software. This read/write bit is
not modified by hardware and its value does not affect hardware.
2
W
Wrap, written by user
0 The next BD is found in the consecutive location
1 The next BD is found at the location defined in X_DES_START.
3
TO2
Transmit software ownership bit
This field is available for use by software. This read/write bit is not modified by hardware and its
value does not affect hardware.
4
L
Last in frame, written by user
0 The buffer is not the last in the transmit frame.
1 The buffer is the last in the transmit frame.
5
TC
Tx CRC, written by user (valid if L = 1)
0 End transmission immediately after the last data byte.
1 Transmit the CRC sequence after the last data byte.
6
DEF
Defer indication, written by FEC (valid if L = 1). Set when the FEC had to defer while trying to
transmit a frame. This bit is not set if a collision occurs during transmission.
7
HB
Heartbeat error, written by FEC (valid if L = 1). Set to indicate that the collision input was not
asserted within the heartbeat window after transmission completed. HB can be set only if
X_CNTRL[HBC] = 1.
8
LC
Late collision, written by FEC (valid if L = 1). Set to indicate that a collision occurred after 56
data bytes were transmitted. The FEC terminates the transmission.
9
RL
Retransmission limit, written by FEC (valid if L = 1). Set to indicate that the transmitter failed
retry limit + 1 attempts to send a message due to repeated collisions.
10–13
RC
Retry count, written by FEC (valid if L = 1). Counts retries needed to successfully send this
frame. If RC = 0, the frame was sent correctly the first time. If RC = 15, the frame was sent
successfully while the retry count was at its maximum value. If RL = 1, RC has no meaning.
14
UN
Underrun, written by FEC (valid if L = 1). If set, the FEC encountered a transmit FIFO underrun
while sending one or more buffers associated with this frame. When a Tx FIFO underrun
occurs, transmission of the frame stops and an incorrect CRC is appended. Any remaining
buffers associated with this frame are accessed and dumped by the transmit logic.
15
CSL
Carrier sense lost, written by FEC (valid if L = 1). Carrier sense dropped out or never asserted
during transmission of a frame without collision.
2
Data
length
Data length, written by user and never by the FEC. Indicates the number of octets the FEC
should send from this BD’s buffer. The DMA engine uses bits 21–31. Bits 16–20 are ignored.
4
Tx buffer
pointer
Tx buffer pointer A[0–31], written by user and never by the FEC. The transmit buffer pointer,
which contains the address of the associated buffer, may be even or odd. The buffer must
reside in external memory.
Содержание PowerQUICC MPC870
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Страница 1162: ...Fast Ethernet Controller FEC MPC885 PowerQUICC Family Reference Manual Rev 2 45 40 Freescale Semiconductor ...
Страница 1172: ...SEC Lite Overview MPC885 PowerQUICC Family Reference Manual Rev 2 46 8 Freescale Semiconductor ...
Страница 1176: ...SEC Lite Address Map MPC885 PowerQUICC Family Reference Manual Rev 2 47 4 Freescale Semiconductor ...
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Страница 1313: ...MPC885 PowerQUICC Family Reference Manual Rev 2 Freescale Semiconductor B 1 Appendix B Serial Communications Performance TBD ...
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