Freescale Semiconductor PowerQUICC MPC870, Справочное руководство

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Instruction and Data Caches
MPC885 PowerQUICC Family Reference Manual, Rev. 2
7-20 Freescale Semiconductor
The data path for the instruction cache and its surrounding logic are shown in Figure 7-9 .
Figure 7-9. Instruction Cache Data Path
The 4-word burst buffer holds the last cache block received from the internal bus (the last miss); the 4-word
block buffer holds the last block retrieved from the instruction cache (the last hit). Note that if one of these
buffers contains the requested instruction, it is also considered a cache hit. To minimize power
consumption, the MPC885 can detect that one of the buffers contains the requested instruction and service
the instruction request from the buffers without activating the instruction cache array.
The MPC885 instruction cache includes the following operational features:
• Instruction fetch latency is reduced by sending the requested instruction address to the instruction
cache and internal bus simultaneously. A cache hit aborts the internal bus transaction before the
MPC885 can initiate an external fetch.
• The instruction cache supports stream hits (allows fetching from the burst buffer or directly from
the internal data bus, before the instruction cache array is filled)
• The instruction cache supports hits under misses (allows servicing hits while a previous miss is
being fetched from the external bus)
4-Word
To Instruction
Internal Data Bus
Set
Address [20–27]
4-Word
Address [28–29]
Instruction Cache
Array Decoder
128
32
Burst
Buffer
128
128
128
Stream
Hit
Mux
2->1
Word
Select
Mux
4->1
128
Data
Bypass
Mux
2->1
32
32
Sequencer
Cache
Block
Buffer