Freescale Semiconductor PowerQUICC MPC870, Справочное руководство

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MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor lxxxv
• Part III, “Configuration and Reset,” describes start-up behavior of the MPC885.
— Chapter 10, “System Interface Unit,” describes the SIU, which controls system start-up,
initialization and operation, and protection, as well as the external system bus.
— Chapter 11, “Reset,” describes the behavior of the MPC885 at reset and start-up.
• Part IV, “Hardware Interface,” describes external signals, clocking, memory control, and power
management of the MPC885.
— Chapter 12, “External Signals,” provides a detailed description of the external signals that
comprise the MPC885 external interface.
— Chapter 13, “External Bus Interface,” describes interactions among signals described in the
previous chapter, including numerous examples and timing diagrams.
— Chapter 14, “Clocks and Power Control,” describes on-chip and external devices, including the
phase-locked loop circuitry and frequency dividers that generate programmable clock timing
for baud-rate generators, timers, and a variety of low-power mode options.
— Chapter 15, “Memory Controller,” describes the memory controller, which control a maximum
of eight memory banks shared between a general-purpose chip-select machine (GPCM) and a
pair of user-programmable machines (UPMs).
— Chapter 16, “PCMCIA Interface,” describes the PCMCIA host adapter module, which
provides all control logic for a PCMCIA socket interface and requires only additional external
analog power-switching logic and buffering.
• Part V, “Communications Processor Module,” describes the configuration, clocking, and operation
of the various communications protocols supported by the MPC885.
— Chapter 17, “Communications Processor Module and CPM Timers,” provides a brief overview
of the MPC885 CPM and a detailed discussion of the clocking mechanisms supported.
— Chapter 18, “Communications Processor,” describes the RISC communications processor
(CP), which handles the low-level communications tasks, freeing the core for higher-level
tasks.
— Chapter 19, “SDMA Channels and IDMA Emulation,” describes the two physical serial DMA
(SDMA) channels on the MPC885 with which the CP implements virtual SDMA channels.
— Chapter 20, “Serial Interface,” describes the serial interface (SI) in which the physical interface
to all SCCs and SMCs is implemented.
— Chapter 21, “Serial Communications Controllers,” describes the serial communications
controllers (SCC), which can be configured independently to implement different protocols for
bridging functions, routers, and gateways, and to interface with a wide variety of standard
WANs, LANs, and proprietary networks.
— Chapter 22, “SCC UART Mode,” describes the MPC885 implementation of the universal
asynchronous receiver transmitter (UART) protocol, used for sending low-speed data between
devices.
— Chapter 23, “SCC HDLC Mode,” describes the MPC885 implementation of the HDLC
protocol.