Freescale Semiconductor PowerQUICC MPC870, Справочное руководство

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ATM Overview
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 36-11
Controlled by the communications processor (CP), the APC provides traffic shaping and offers a fair
queueing mechanism for port-to-port cells in-transit. Thus, the APC can flexibly combine SAR traffic with
PTP traffic (cell switching). The pace controller is based on multiple-level circular tables (APC scheduling
tables) in the dual-port RAM that are used to queue transmission of all the active channels.
The operation of the APC is controlled by several input parameters programmed by the user. Scheduling
of traffic is controlled through the APC scheduling table length, the number of cells to be selected in an
APC slot time, and the APC request timer. The period of the APC request timer determines the length of
an APC slot time.
The APC can handle multiple priority levels defined by the user with each level containing an APC
scheduling table and an optional PTP queue. The first level is serviced with the highest priority and the last
is serviced with the lowest priority; that is, channels in the second and lower levels are serviced only as
bandwidth becomes available. Channels with a low tolerance for cell delay variation (CDV), such as
real-time traffic, should be placed in the upper levels (higher priority). The lower priority levels can be
used for non-real-time traffic, such as UBR channels.
The APC pace parameters, such as PCR, SCR, and BT, and the priority of each channel are programmed
by the user prior to the activation command according to the traffic service (CBR, VBR or UBR) selected
for the channel number. For ABR transmission, the host adjusts the APC parameters in response to
incoming resource management (RM) cells and defines the ABR available cell rate (ACR). The APC
period can be changed on the fly, thereby allowing the bit rate for a channel to be changed dynamically,
which is necessary to control transmission of traffic types such as ABR. For ABR, it is the user’s
responsibility to evaluate RM cells and update the APC pace values in the TCT.
The APC input parameters are described in Chapter 40, “ATM Pace Control.” These parameters define the
minimum and maximum cell rate and cell delay variation.
36.9 Internal and External Channels (Extended Channel Mode)
Internal channels are the channels numbered 0 through 31; external channels have channel numbers greater
than 31. The external channels become available only when the user selects extended channel mode, see
Section 38.2, “SAR Receive State Register (SRSTATE),” and Section 37.4 “SAR Transmit State Register
(STSTATE).”
The TCTs and RCTs for internal channels are directly accessed in the (internal) dual-port RAM. For
external channels, the TCT and RCT structures are placed in external memory and thus require DMA
accesses to read and update. Also, the GFC/VPI/VCI/PTI mapping for external channels requires a CAM
or address compression method instead of the generally faster dual-port RAM look-up table method used
for internal channels. Therefore, the bit rate supported in extended channel mode is reduced. The overall
throughput depends on the number of external channels and the bit rate ratio between external and internal
channels; that is, higher bit rate channels should be assigned internal channel numbers.
36.10 ATM Port-to-Port (PTP) Cell Switching
The PTP mechanism allows the user to implement ATM to ATM cell switching from one ATM port to
another ATM port (including specific PHYs on the UTOPIA multi-PHY bus).
Figure 36-3 shows an