Freescale Semiconductor PowerQUICC MPC870, Справочное руководство

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MPC885 PowerQUICC Family Reference Manual, Rev. 2
lxxxiv Freescale Semiconductor
Audience
This manual is intended for software and hardware developers and application programmers who want to
develop products for the MPC885. It is assumed that the reader has a basic understanding of computer
networking, OSI layers, and RISC architecture. In addition, it is assumed that the reader has a basic
understanding of the communications protocols described here. Where it is considered useful, additional
sources are provided that provide in-depth discussions of such topics.
Organization
Following is a summary and a brief description of the chapters of this manual:
• Part I, “Overview,” provides a high-level description of the MPC885, describing general operation
and listing basic features.
— Chapter 1, “MPC885 Overview,” provides a high-level description of MPC885 functions and
features. It roughly follows the structure of this book, summarizing the relevant features and
providing references for the reader who needs additional information.
— Chapter 2, “Memory Map,” presents a table showing where MPC885 registers are mapped in
memory. It includes cross references that indicate where each register is described in detail.
• Part II, “MPC8xx Microprocessor Module,” describes the MPC8xx core. These chapters provide
details concerning the processor core as an implementation of the PowerPC architecture.
— Chapter 3, “The MPC8xx Core,” provides an overview of the MPC885 core.
— Chapter 4, “MPC8xx Core Register Set,” describes the hardware registers accessible to the
MPC885 core. These include both architecturally-defined and MPC885-specific registers.
— Chapter 5, “MPC885 Instruction Set,” describes the PowerPC instructions implemented by the
MPC885. These instructions are organized by the level of architecture in which they are
implemented—UISA, VEA, and OEA.
— Chapter 6, “Exceptions,” describes the PowerPC exception model as it is implemented on the
MPC885.
— Chapter 7, “Instruction and Data Caches,” describes the organization of the on-chip instruction
and data caches, cache control, various cache operations, and the interaction between the
caches, the load/store unit (LSU), the instruction sequencer, and the system interface unit
(SIU).
— Chapter 8, “Memory Management Unit,” describes how the PowerPC MMU model is
implemented on the MPC885. Although the MPC885 MMU is based on the PowerPC MMU
model, it differs greatly in many respects, which are described in this chapter.
— Chapter 9, “Instruction Execution Timing,” describes the MPC885 instruction unit, and
provides ways to take greatest advantage of its RISC architecture characteristics, such as
pipelining and parallel execution. It includes a table of instruction latencies and lists
dependencies and potential bottlenecks.