Freescale Semiconductor PowerQUICC MPC870, Справочное руководство

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Clocks and Power Control
MPC885 PowerQUICC Family Reference Manual, Rev. 2
14-6 Freescale Semiconductor
The OSCLK can be supplied by either a crystal or an external clock oscillator. Crystals are typically much
cheaper than clock oscillators; however, a clock oscillator has significant design advantages over a crystal
circuit in that clock oscillators are easier to work with, resulting in faster design, debugging, and
production.
14.2.3 DPLL Reset Configuration
While PORESET is asserted, the reset configuration of the DPLL is sampled on the MODCK[1:2] pins.
The DPLL immediately begins to use the multiplication factor and pre-division factor values and external
clock source for OSCLK determined by the sampled MODCK[1:2] pin and attempts to achieve lock;
therefore, the MODCK[1:2] signals should be maintained steadily throughout PORESET assertion. The
mode selection field and various factors are set as shown in
Table 14-3 . After PORESET is negated, the
MODCK[1:2] values are internally latched, and the signals applied to MODCK[1:2] can be changed.
Table 14-2. Typical System Frequency Generation
Input
Frequency
(MHz) (f
ref
)
PDF MFI MFN
1
1
For MFN = 0, EXTCLK will be synchronized to CLKOUT.
MFD dpgdck
PLPRCR
S[10:11] JDBCK
General System
Frequency
(MHz) [GCLK2]
2
2
Assuming DFNH = 0 and CSR = 0.
10 0 8 0 0 160 1 80 40
10 0 9 6 9 192 1 96 48
10 0 10 4 9 208 1 104 52
10 0 13 2 9 264 1 132 66
10 0 15 0 0 300 1 150 75
10 0 10 0 0 200 0 200 100
10 0 13 3 9 266 0 266 133
45 3 8 0 0 180 1 90 45
45 2 8 1 2 250 0 250 125
50 2 9 0 0 300 1 150 75
50 1 5 2 6 264 0 264 132
66 2 6 0 1 264 1 132 66
66 2 6 0 1 264 0 264 132