Freescale Semiconductor PowerQUICC MPC870, Справочное руководство

Страница: 273 / 1426

Memory Management Unit
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor 8-31
8.9 Memory Management Unit Exceptions
Table 8-23 describes MPC885-specific MMU exceptions.
8.10 TLB Manipulation
The TLBs can be updated in several ways. The TLB reloading process is primarily performed in software
with some hardware assistance. The TLB replacement counter can be configured to select only from the
first 28 entries in each TLB. TLBs can be invalidated by using the tlbie and tlbia instructions.
8.10.1 TLB Reload
The TLB reload (tablewalk) function is performed in the software with some hardware assistance. It
consists of the following actions:
• Automatic storage of the missed data or instruction EA and default attributes in MI_EPN or
MD_EPN. This value is loaded into the selected entry on a write to MI_RPN or MD_RPN.
• Automatic updating of the replacement location counter to point to the entry to be replaced. This
value is placed in the index field in MI_CTR and MD_CTR.
• As Figure 8-4 and Figure 8-5 show, the level-one pointer is generated when an mfspr[M_TWB] is
performed by concatenating the level-one table base with the level-one index.
• The level-two pointer is generated when an mfspr[MD_TWC] is performed by concatenating the
level-two table base (extracted from the level-one table) with the level-two index.
• The TLB entry is written by loading the tablewalk level-two entry value to Mx_RPN.
• A scratch register, M_TW, is provided in addition to the architecture-defined SPRG0–SPRG3, so
miss code need not corrupt existing GPRs.
Table 8-23. MPC885-Specific MMU Exceptions
Exception Cause
ITLB miss MSR[IR] = 1 and an attempt is made to fetch an instruction from a page whose EPN cannot be translated
by the ITLB. Tablewalk software is responsible for loading information for the missed page from the
translation table. See
Section 8.10.1.1, “Translation Reload Examples,” and Section 6.1.3.2, “Instruction
TLB Miss Exception (0x01100).”
DTLB miss MSR[DR] = 1 and an attempt is made to access a page whose EPN cannot be translated by the DTLB.
Tablewalk software is responsible for loading translation information for the missed page from the
translation table. See
Section 8.10.1.1, “Translation Reload Examples,” and Section 6.1.3.3, “Data TLB
Miss Exception (0x01200).”
ITLB error The EA cannot be translated and the level-one segment or page valid bit is zero in the translation table,
the fetch access violates memory protection, or the fetch access is to guarded memory and MSR[IR]
= 1.
The exact exception cause is found in SRR1. Table 6-15 describes bit assignments. If needed, it is
software’s responsibility to invoke the ISI exception handler.
DTLB error MSR[DR] = 1 and the EA of a load, store, icbi , dcbz , dcbst , dcbf , or dcbi cannot be translated and
either the level-one segment or page valid bit are zero in the translation table, the access violates
memory protection, or an attempt is made to write to a page with a negated change bit.
The DSISR explains invocation of the DTLB error exception handler.
Table 6-16 describes bit
assignments. If needed, it is software’s responsibility to invoke the DSI exception handler.