Toshiba TMPR7901, User Manual

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Chapter 7: C790 Bus/G-Bus Bridge
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
7-18
7.6.20 G- Bus Broken Master Latency Timer
The latency timer specifies the maximum period in which the master has to claim the G-bus
after the G-bus is granted. The counter is decremented at every B-Bus clock cycle. The
counter starts counting down when the arbiter asserts the grant signal. If the counter is down
to zero and the master device does not respond, an interrupt is signaled to the C790, and
the corresponding master status bit is set.
63 32
0
32
31 8 7 0
0
GBBMLT
24 8
Table 7-22 G-Bus Broken Master Latency Timer
Bits Field R/W Description Initial Value
63:8 – R/O
Reserved. Must be written as zeroes, and
returns zeroes when read.
0
7:0 GBBMLT R/W
G-Bus Broken Master Latency Timer. Is
counted down by the G-Bus clock.
0xFF
7.6.21 G- Bus Slave Latency Timer
The slave latency timer specifies the maximum period in which the slave must acknowledge
the master. The counter is decremented at every G-Bus clock. The counter starts counting
down when the master asserts the STARTB signal. If the counter is down to zero and the
slave device does not respond, a G-Bus error is generated and the master generates an
interrupt signal to inform the C790.
63 32
0
32
31 16 15 0
0 GBSLT
16 16
Table 7-23 G-Bus Slave Latency Timer
Bits Field R/W Description Initial Value
63:16 – R/O
Reserved. Must be written as zeroes, and
returns zeroes when read.
0
15:0 GBSLT R/W
Latency Timer. Is counted down by the G-
Bus clock.
0xFFFF