Chapter 17: Pins
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
17-3
Name of Signal
I/O
Function
MAC1_MDC
O
MII Management Clock
MAC1_MDIO
I/O
MII Management Data Input/Output
MAC1_HwFDupSel
I
Full Duplex Select
Timer/Counter Interface
TIMOUT1
O
Timer 1 Output
TIMIN1
I
External Clock Input for Timer 1
TIMOUT2
O
Timer 2 Output
TIMIN2
I
External Clock Input for Timer 2
Serial Peripheral Interface
SPI_MISO
I
Serial Data Input
SPI_MOSI
O
Serial Data Output
SPI_Clk
O
SPI Data Clock
SPI_Port0B
O
SPI Chip select for SPI device 0
SPI_Port1B
O
SPI Chip select for SPI device 1
SPI_Port2B
O
SPI Chip select for SPI device 2
SPI_Port3B
O
SPI Chip select for SPI device 3
SPI_Port4B
O
SPI Chip select for SPI device 4
SPI_Port5B
O
SPI Chip select for SPI device 5
PCI0 Interface
PCI0_AD[31:0]
I/O
The 64 Bit Address and Data Buses are multiplexed on the same PCI pins.
PCI0_CBEB[3:0]
I/O
Command and Byte Enable
PCI0_PAR
I/O
Parity for PCI_AD[31:0] and PCI_CBE[3:0]B Even Parity
PCI0_FRAMEB
I/O
Indicates beginning and duration of a transaction.
PCI0_TRDYB
I/O
Target Ready
PCI0_IRDYB
I/O
Initiator Ready
PCI0_STOPB
I/O
PCI_STOPB Indicates that the current Target is requesting Initiator to stop the
current transaction.
PCI0_DEVSELB
I/O
Device select; it indicates that the current driving device has decoded its address
as the target of the current access.
PCI0_CLK
I
PCI Clock Input
PCI0_PERRB
I/O
Data Parity Error
Reporting parity error on all transactions except Special Cycle command.
PCI0_IDSEL
I
Initialization Device Select
It is used as a chip select during configuration read/write transaction on PCI bus.
PCI0_SERRB
O
System Error
Reporting errors for all the address parity errors and data parity error on Special
Cycle commands, and may optionally be used on any other non-parity or system
errors.
PCI0_REQB
O
PCI0 request signal to PCI arbiter
PCI0_GNTB
I
PCI0 bus Grant form PCI arbiter
PCI0_GNT0B
I
PCI0 bus Grant 0B
PCI0_REQ1B
O
PCI0 Request 1B
PCI0_GNT1B
I
PCI0 bus Grant 1B
PCI0_REQ2B
O
PCI0 Request 2B
PCI0_GNT2B
I
PCI0 bus grant 2B
PCI1_REQ1B_PCI0_REQ3B
O
PCI1 Request 1B Multiplex with PCI10 Request 3B
PCI1_REQ2B_PCI0_REQ4B
O
PCI1 Request 2B Multiplex with PCI10 Request 4B
PCI0_RSTB
I
PCI0 Reset signal
PCI1 Interface
PCI1_AD[31:0]
I/O
The 64 Bit Address and Data Buses are multiplexed on the same PCI pins.
PCI1_CBEB[3:0]
I/O
Command and Byte Enable
PCI1_PAR
I/O
Parity for PCI_AD[31:0] and PCI_CBEB[3:0] Even Parity
PCI1_FRAMEB
I/O
Indicates beginning and duration of a transaction.
Summary of Contents for TMPR7901
Page 1: ...TX System RISC TX79 Family TMPR7901 Symmetric 2 way superscalar 64 bit CPU ...
Page 14: ...Handling Precautions ...
Page 15: ......
Page 17: ...1 Using Toshiba Semiconductors Safely 1 2 ...
Page 41: ...4 Precautions and Usage Considerations 4 2 ...
Page 42: ...TX7901 User s Manual Rev 6 30T November 2001 DOCUMENT NUMBER M 99 00004 07 ...
Page 43: ......
Page 259: ...Chapter 13 Removed TX7901 User s Manual Rev 6 30T Nov 2001 13 1 13 Removed ...
Page 260: ...Chapter 13 Removed TX7901 User s Manual Rev 6 30T Nov 2001 13 2 ...