Toshiba TMPR7901, User Manual

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Chapter 16: Clocks
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
16-5
16.3 Operation
The TX7901 relies on one external reference clock source (refClk) and on-chip phased-
locked loop for generating various clocks, as shown in the above Figure. pllSel[1:0]) signals
are used to select either PLL or bypass PLL.
Table 16-2 PLL Selection
PllSel[1:0] Clock Source
00 PLL
01 Reserved
10 Reserved
11 Bypass PLL (test mode)
The PLL generates the overall system operating frequency in integer multiples of the input
clock frequency. For special purposes (e.g., test mode), it is possible to disable the PLL, in
which case the external reference clock is used as the system operating clock. This mode
must not be used as a normal operating mode. Its only valid use is for low-frequency silicon
debugging.
The PLL also functions as a multiplier to the cpuClk:sysClk ratios in addition to de-skewing
the SDRAMC clock and the external SDRAM clock. During normal operation, refClk is
always in sync with sysClk so that the external SDRAM and TX7901 SDRAM controller are
running at the same system bus frequency.
The TX7901 also provides a following of clock dividers for cpuClk:sysClk gear ratios. These
values of the divider selector (divSel[1:0]) I/O pins are sampled at Reset only.
Table 16-3 Clock Gear Ratio
DivSel[1:0] CpuClk:sysClk Gear Ratio
00 Divide by 1 (test mode)
01 Divide by 2
10 Divide by 3
11 Divide by 4
For sysClk:gbusClk, only the gear ratio of 2:1 is supported for normal operations. In the test
mode all clock domains in the chip run at the same frequency.