Toshiba TMPR7901, User Manual

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Chapter 14: UARTS WITH FIFOS
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
14-8
14.4.5 Line Status Registers (LSR0,LSR1)
Table 14-6 lists the fields of the Line Status Registers.
Table 14-6 Line Status Register Fields
Bit Read Comment
0 DR Data Ready
1 OE Overrun Error
2 PE Parity Error
3 FE Framing Error
4 BI Break Interrupt
5 THRE TX Holding Register Empty
6 TEMT Transmitter Empty
7 FIFOERR RX Data Error in FIFO
After reset, bits 0 to 4 and bit 7 are all “0,” while bits 5 and 6 are set to “1.”
This register is read only.
Note: This register is reset asynchronously.
14.4.5.1 DR – Data Ready
This bit is set either by the RX Buffer becoming full or by a byte being transferred into the
FIFO. It is cleared by the G-Bus reading the RX Buffer or by reading all of the FIFO bytes.
This bit is also cleared whenever the FIFO enable bit is changed.
14.4.5.2 OE – Overrun Error
If the FIFOs are disabled, this bit is set if the RX Buffer was not read by the G-Bus before
new data from the RX Shift Register overwrote the previous contents. OE is cleared when
the G-Bus reads this register.
If the FIFOs are enabled, an overrun error occurs when the RX FIFO is full and the RX Shift
Register becomes full. OE is set as soon as this happens. The character in the Shift
Register is then overwritten, but is not transferred to the FIFO.
14.4.5.3 PE – Parity Error
If the FIFOs are disabled, this bit is set if the received data do not have a valid parity bit.
This bit is reset when the G-Bus reads this register.
If the FIFOs are enabled, the state of this bit is revealed to the G-Bus when the byte it refers
to is at the top of the FIFO.