Toshiba TMPR7901, User Manual

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Chapter 12: 10/100 IEEE802.3 Media Access Controller
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
12-46
This time the loop goes deeper than the previous case, including the MAC block. Status bits
and counters are all active.
To do a loop back test, the MAC should be set in the full-duplex mode.
12.5.2.3 TxFIFO Specific Function
The TxFIFO provides the mechanism for sending frame data through the MAC and onto the
network. FIFO input is controlled by the DMA.
Transmission of a frame starts automatically either when a certain number of words is
written to the TxFIFO or when EOF is written. This threshold (TxSOFTh) is in the TFCReg.
If the FIFO runs out of data before EOF is detected, the partial frame is transmitted with an
incorrect CRC, regardless of the state of the CRC bit in the transmit frame configuration
register. If an Underflow occurs before 64 bytes have been transmitted, a fragment is
transmitted. When an Underflow occurs while writing data to TxFIFO, the host must still
delineate the frame by asserting EOF. Data written to the TxFIFO after the Underflow and
before EOF will be ignored.
12.5.2.3.1 Collision Retransmission
The TxFIFO does not overwrite the first 64 bytes of a frame until they are transmitted
successfully. In the event of a collision, the FIFO pointers are reset to the beginning of the
frame. These bytes are retransmitted after a collision back-off period has elapsed.
12.5.2.3.2 Half-Duplex Flow Control
While in the half-duplex mode, the host system can have the transmitter force a collision by
asserting TxEn every time a frame is received. MAC will transmit the preamble and 32 bits
of jam bytes then release TxEn. This allows all stations on the network to see the collision
and backoff.
MAC can also be configured to assert flow control when the RxFIFO overflows.
12.5.2.3.3 Full-Duplex Flow Control
If the RxFCEn bit in the reception frame configuration register is set, the reception FIFO
overflows, and the port is configured for full-duplex, the MAC will generate then transmit a
pause frame. Only one pause frame is sent when the FIFO overflows.
The MAC also responds to received flow control frames.
12.5.2.3.4 CRC Generation
The MAC has the capability of calculating and appending the cyclic redundancy check
(CRC) to each transmitted frame. This is selectable by the bit in the TFCReg or Descriptor.
If the CRC bit is set, every frame has the CRC calculated and appended. Otherwise, no
CRC is calculated and appended.