Toshiba TMPR7901, User Manual

Page: 227 / 309

Chapter 12: 10/100 IEEE802.3 Media Access Controller
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
12-19
Bit(s) Field R/W Description
7 TxC511 R/W Frames Transmitted (256~511 byte) Counter Overflow (0)
6 TxC255 R/W Frames Transmitted (128~255 byte) Counter Overflow (0)
5 TxC127 R/W Frames Transmitted (65~127 byte) Counter Overflow (0)
4 TxC64 R/W Frames Transmitted (64 byte) Counter Overflow (0)
3 TxCBC R/W Broadcast Frames Transmitted Counter Overflow (0)
2 TxCMC R/W Multicast Frames Transmitted Counter Overflow (0)
1 TxCFrm R/W Total Good Frames Transmitted Counter Overflow (0)
0 TxCByte R/W Total Bytes Transmitted Counter Overflow (0)
12.3.1.8 Receive Interrupt Mask Register (RIMReg)
The bits of the Receive Interrupt Mask Register enable the corresponding interrupt bits of
the Receive Interrupt Register to cause an interrupt. When a receive event occurs or a
counter overflows, it sets one of the bits in the Receive Interrupt Register, and the macgIntB
signal becomes active if the corresponding enable bit in this register is set to 1. When any
bit in this register is 0 and the corresponding bit is set to 1 in the Receive Interrupt Register,
it is masked (hidden), preventing it from driving the macgIntB signal and causing an interrupt.
Upon the completion of reset, this register‘s value is 0x0000_0000.
31 25 24 23 22 21 20 19 18 17 16
0
RxFB
ErrM
Rx
Stop
M
Rx
Read
FrmM
Rx
Buf
ErrM
RxF
Overf
M
RxC
NoFi
FM
RxC
No
DesM
RxC
JabM
ExC
Frag
M
7 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxC
Unds
M
RxC
NoAln
M
RxC
CRC
M
RxC
ErrM
RxC
Long
M
RxC
Pause
M
RxC
Gt1K
M
RxC
1KM
RxC
511M
RxC
255M
RxC
127M
RxC
64M RxC
BCM
RxC
MCM
RxC
FrmM
RxC
Byte
M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Table 12-15 RIMReg Register Field Descriptions
Bit(s) Field R/W Description
31:25 – R/O Reserved (0x00)
24 RxFBErrM R/W Receive Fatal Bus Error Mask (0)
23 RxStopM R/W Receive Stopped Mask (0)
22 RxReadFrmM R/W A Readable Frame received Mask (0)
21 RxBufErrM R/W Truncated Frame due to no more Descriptor Mask (0)
20 RxFOverfM R/W Receive FIFO Overflow Error Mask (0)
19 RxCNoFiFM R/W No RxFIFO Missed Frames Counter Overflow Mask (0)
18 RxCNoDesM R/W No RxDescriptor Missed Frame Counter Overflow Mask (0)
17 RxCJabM R/W Jabber Frames Received Counter Overflow Mask (0)
16 ExCFragM R/W Fragments Received Counter Overflow Mask (0)
15 RxCUndsM R/W Undersized Frames Counter Overflow Mask (0)
14 RxCNoAlnM R/W Misaligned Frames Counter Overflow Mask (0)
13 RxCCRCM R/W Frames Received with Bad CRC Counter Overflow Mask (0)
12 RxCErrM R/W Receive Errors Counter Overflow Mask (0)
11 RxCLongM R/W Long Frames Received Counter Overflow Mask (0)
10 RxCPauseM R/W MAC Pause Frames Received Counter Overflow Mask (0)
9 RxCGt1KM R/W Frames Received (1024~max byte) Counter Overflow Mask (0)
8 RxC1KM R/W Frames Received (512~1023 byte) Counter Overflow Mask (0)