Toshiba TMPR7901, User Manual

Page: 275 / 309

Chapter 14: UARTS WITH FIFOS
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
14-15
14.4.10.5 DDCD – Delta Data Carry Detect
This bit is set (“1”) if the state of DCD has changed since the Modem Status Register was
last read.
14.4.10.6 TERI – Trailing Edge Ring Indicator
This bit is set if the RI* input has changed from “0” to “1” since this register was last read.
14.4.10.7 DDSR – Delta Data Set Ready
This bit is set (“1”) if the state of DSR has changed since this register was last read.
14.4.10.8 DCTS – Delta Clear To Send
This bit is set (“1”) if the state of CTS has changed since this register was last read.
14.4.10.9 MSR RESET and SAMPLE TIMING
After reset bits D0 through D3 are “0” and can be written to, and bits D4 through D7 are
inputs.
A modem status interrupt can be cleared by writing “0,” or set by writing “1” to this register.
A change in any of the modem status input signal levels will be sampled twice by gbsBusClk
before there is any change to the Modem Status Register value.
14.4.11 Scratch Registers (SCR0, SCR1)
This is a general-purpose read/write register. After reset, the content of this register is
undefined.
14.4.12 Pre-scalar Register
The incoming clock gbsBusClk (provided by the 66/50 MHz TX7901 clock) is divided by the
value held in the pre-scalar registers to produce the prescaler output signal, which is then
passed onto the Baud Rate Generator.