Chapter 12: 10/100 IEEE802.3 Media Access Controller
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
12-18
Bit(s)
Field
R/W
Description
10
TxCPauseM
R/W
MAC Pause Frames Transmitted Counter Overflow Mask (0)
9
TxCGt1KM
R/W
Frames Transmitted (1024~max byte) Counter Overflow Mask (0)
8
TxC1KM
R/W
Frames Transmitted (512~1023 byte) Counter Overflow Mask (0)
7
TxC511M
R/W
Frames Transmitted (256~511 byte) Counter Overflow Mask (0)
6
TxC255M
R/W
Frames Transmitted (128~255 byte) Counter Overflow Mask (0)
5
TxC127M
R/W
Frames Transmitted (65~127 byte) Counter Overflow Mask (0)
4
TxC64M
R/W
Frames Transmitted (64 byte) Counter Overflow Mask (0)
3
TxCBCM
R/W
Broadcast Frames Transmitted Counter Overflow Mask (0)
2
TxCMCM
R/W
Multicast Frames Transmitted Counter Overflow Mask (0)
1
TxCFrmM
R/W
Total Good Frames Transmitted Counter Overflow Mask (0)
0
TxCByteM
R/W
Total Bytes Transmitted Counter Overflow Mask (0)
12.3.1.7 Transmit Interrupt Register (TIReg)
The Transmit Interrupt Register has the interrupt events. If an event occurs whose interrupt
is enabled by setting the corresponding mask bit in the Transmit Interrupt Mask Register, it
causes an interrupt. This register is automatically cleared to zero after being read. Upon the
completion of reset, this register’s value is 0x0000_0000.
31
26
25
24
23
22
21
20
19
18
17
16
0
TxFB
Err
Tx
Stop
Tx
Good
Tx
LCol
TxEx
Def
TxEx
Col
TxF
Undf
TxC
Undf
TxC
Rty
ExC
Def
6
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TXCL
Col
TxCM
Col
TxCS
Col
TxC
Col
TxC
Long
TxC
Pause
TxC
Gt1K
TxC
1K
TxC
511
TxC
255
TxC
127
TxC
64
TxC
BC
TxC
MC
TxC
Frm
TxC
Byte
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 12-14 TIReg Register Field Descriptions
Bit(s)
Field
R/W
Description
31:26
–
R/O
Reserved (0x00)
25
TxFBErr
R/W
Transmit Fatal Bus Error (0)
24
TxStop
R/W
Frame Transmission Stopped or suspended (0)
23
TxGood
R/W
A Good Frame Transmitted (0)
22
TxLCol
R/W
Late Collision (0)
21
TxExDef
R/W
Excessive Deferral (0)
20
TxExCol
R/W
Collision Error (0)
19
TxFUndf
R/W
Transmit FIFO Underflow Error (0)
18
TxCUndf
R/W
Transmit Underflows Counter Overflow (0)
17
TxCRty
R/W
Transmit Retry Errors Counter Overflow (0)
16
ExCDef
R/W
Excessive Deferrals Counter Overflow (0)
15
TxCLCol
R/W
Late Collisions Counter Overflow (0)
14
TxCMCol
R/W
Multiple Collision Counter Overflow (0)
13
TxCSCol
R/W
Single Collision Counter Overflow (0)
12
TxCCol
R/W
Total Collision Counter Overflow (0)
11
TxCLong
R/W
Long Frames Transmitted Counter Overflow (0)
10
TxCPause
R/W
MAC Pause Frames Transmitted Counter Overflow (0)
9
TxCGt1K
R/W
Frames Transmitted (1024~max byte) Counter Overflow (0)
8
TxC1K
R/W
Frames Transmitted (512~1023 byte) Counter Overflow (0)
Summary of Contents for TMPR7901
Page 1: ...TX System RISC TX79 Family TMPR7901 Symmetric 2 way superscalar 64 bit CPU ...
Page 14: ...Handling Precautions ...
Page 15: ......
Page 17: ...1 Using Toshiba Semiconductors Safely 1 2 ...
Page 41: ...4 Precautions and Usage Considerations 4 2 ...
Page 42: ...TX7901 User s Manual Rev 6 30T November 2001 DOCUMENT NUMBER M 99 00004 07 ...
Page 43: ......
Page 259: ...Chapter 13 Removed TX7901 User s Manual Rev 6 30T Nov 2001 13 1 13 Removed ...
Page 260: ...Chapter 13 Removed TX7901 User s Manual Rev 6 30T Nov 2001 13 2 ...