Toshiba TMPR7901, User Manual

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Chapter 14: UARTS WITH FIFOS
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
14-10
14.4.6 FIFO Control Registers (FCR0, FCR1)
Table 14-7 lists the fields of the FIFO Control Registers. These fields control the clearing
and enabling of the FIFOs as well as the Receive FIFO Trigger level and DMA mode 1.
Table 14-7 FIFO Control Register Field Descriptions
Bit(s) Write Comment
0 FIFOE Enable FIFOs
1 CLRR Clear RX FIFO
2 CLRT Clear TX FIFO
3 DMA1 Set DMA mode 1
4,5 “X” Reserved for future use
6 RFTL0 RX FIFO Trigger Level Bit 0
7 RFTL1 RX FIFO Trigger Level Bit 1
14.4.6.1 FIFOE – FIFO Enabled
Writing a “1” to this bit enables both the RX and TX FIFOs. When the FIFOs are either
enabled or disabled, both the RX and the TX FIFOs are reset.
This bit must be a “1” for any of the other bits in the register to have any effect.
14.4.6.2 CLRR – Clear Receive FIFO
Writing a “1” to this bit clears all the bytes in the RX FIFO and resets its counter logic. The
RX Shift Register is not affected. This bit is self-clearing.
14.4.6.3 CLRT – Clear Transmit FIFO
Writing a “1” to this bit clears all the bytes in the TX FIFO and resets its counter logic. The
TX Shift Register is not affected. This bit is self-clearing.
14.4.6.4 DMA1 – DMA Mode 1
This bit determines the DMA mode which the TXRDY and RXRDY pins support.
On reset, or when this bit is cleared, the device operates in DMA Mode 0. When this bit is
set, the device operates in DMA Mode 1. This bit has no effect unless the FIFOE bit is set as
well.
TXRDY – Mode 0: Goes active (Low) when the TX FIFO or the TX Holding Register is
empty. Becomes inactive when a byte is written to the Transmit
channel.
TXRDY – Mode 1: Goes active (Low) when there is at least one unfilled position in the TX
FIFO. Becomes inactive when the TX FIFO is full.
RXRDY – Mode 0: Becomes active (Low) when there is at least one character in the RX
FIFO or the RX Holding Register is full. It become inactive when there
are no more characters in the RX FIFO or the RX Holding Register.