Toshiba TMPR7901, User Manual

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Chapter 10: Programmable Timer/Contents
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
10-5
Signal Name I/O Description
output is connected to Interrupt 6 of the Interrupt Controller. This output will be
asserted when the Max Count is reached, and will remain asserted until the proper
registers are written to (to de-assert it), or until the C790 is Reset.
tmrgInt1B O
Active Low output for Timer 1 when it is configured as a Periodic Interval Timer. Timer
1 is configured as a Periodic Interval Timer by writing to its configuration register. This
output is connected to Interrupt 7 of the Interrupt Controller. This output will be
asserted when the Max Count is reached, and will remain asserted until the proper
registers are written to (to de-assert it), or until the C790 is Reset.
tmrgInt2B O
Active Low output for Timer 2 when it is configured as a Periodic Interval Timer. Timer
2 is configured as a Periodic Interval Timer by writing to its configuration register. This
output is connected to Interrupt 8 of the Interrupt Controller. This output will be
asserted when the Max Count is reached, and will remain asserted until the proper
registers are written to (to de-assert it), or until the C790 is Reset.
TIMOUT1* O
Active Low output of Timer 1 when it is configured as a Pulse Generator. This output
is exclusively used by devices outside of the TX7901. It is connected to an I/O pad
output buffer for this purpose. Both the duty cycle and the frequency of the pulse
generated on this output are programmable by writing appropriate values to the
respective timer’s configuration registers.
TIMOUT2* O
Active low output of Timer 2 when it is configured as a Pulse Generator. This output is
exclusively used by devices outside of the TX7901. It is connected to an I/O pad
output buffer for this purpose. Both the duty cycle and the frequency of the pulse train
generated from this output are programmable by writing appropriate values to the
respective timer’s configuration registers.
tmrwdtreq2B O
Active Low output of Timer 2 when configured as a Watchdog Timer. This output is
demultiplexed onto either the NMI input or the Master Reset input of the TX7901, and
the demultiplexer is controlled by bit 16 of the Watchdog Mode Register.
tmrgdata[63:0] O
Data bus output from the Timer to the G-Bus. The Timer drives this bus to
0xFFFF_FFFF when there are no data to output to the G-Bus. In other cases, the
Timer only drives bits [31:0] of this bus.
10.4 Configuration Registers
Table 10-3 lists the addresses of the registers that configure the operation of the three
TX7901 Timer/Counters when written to. Detailed descriptions of the fields of each of these
registers appear in the following sub-sections. Register functionality and operation is
discussed in Section 10.5 in addition to discussing Timer/Counter Operation.
Table 10-3 Timer/Counter Configuration Registers
Register Name Timer 0 Timer 1 Timer 2
R/W Address
Field
Name
Address
Field
Name
Address
Field
Name
Timer Control Register R/W 0x1E00_4000 TMTCR0 0x1E00_4100 TMTCR1 0x1E00_4200 TMTCR2
Timer Interrupt Status Register R/W 0x1E00_4004 TMTISR0 0x1E00_4104 TMTISR1 0x1E00_4204 TMTISR2
Compare Register A R/W 0x1E00_4008 TMCPRA0 0x1E00_4108 TMCPRA1 0x1E00_4208 TMCPRA2
Compare Register B R/W 0x1E00_400C TMCPRB0 0x1E00_410C TMCPRB1 0x1E00_420C TMCPRB2
Interval Timer Mode Register R/W 0x1E00_4010 TMITMR0 0x1E00_4110 TMITMR1 0x1E00_4210 TMITMR2
Divider Register R/W 0x1E00_4020 TMCCDR0 0x1E00_4120 TMCCDR1 0x1E00_4220 TMCCDR2
Pulse Generator Mode Register R/W Reserved Reserved 0x1E00_4130 TMPGMR1 0x1E00_4230 TMPGMR2
Watch Dog Timer Mode Register R/W Reserved Reserved Reserved Reserved 0x1E00_4240 TMWTMR2
Timer Read Register R/O 0x1E00_40F0 TMTRR0 0x1E00_41F0 TMTRR1 0x1E00_42F0 TMTRR2
Note: Accessing registers that are marked “Reserved” will result in unknown behavior. All registers must be accessed
as 32-bit quantities.