Toshiba TMPR7901, User Manual

Page: 305 / 309

Chapter 17: Pins
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
17-1
17. Pins
This chapter details the physical pins of the TX7901. Table 17-1 describes the functionality
of each group of pins, while Table 17-2 specifies the allocation of pin positions for each
individual signal.
Table 17-1 TX7901 Pin Functionality
Rev.2.0 pinout
Name of Signal I/O Function
System Bus Interface
MasterReset I Master Reset
BigEndian I Input signal to select for Big-Endian or Little Endian at power up.
DPCI_SPCI_SEL I
To select between different options of TX7901
1: Select Dual PCI
0: Select Single PCI
Interrupt Interface
NMIB I Non-Maskable Interrupt
INT_MAC0B I External Interrupt from ether MAC PHY0
INT_MAC1B I External Interrupt from ether MAC PHY1
INT_0B I External Interrupt Request 0
INT_1B I External Interrupt Request 1
INT_2B I External Interrupt Request 2
INT_3B I External Interrupt Request 3
INT_4B I External Interrupt Request 4
Clock Interface
PLL_DIV0, PLL_DIV1 I
To set up divide Ratio between CPU clock to internal System Bus Clock,
00: Divide By 1 (Test only)
01: Divide by 2
10: Divide by 3
11: Divide by 4
PLL_TestOut O PLL Test
PLL_RefCLK I Reference clock source to drive CPU clock and other internal clocks of TX7901.
PLL_SyncIn I External PLL Synch In signal
PLL_Sel0 I PLL Select
PLL_Sel1 I PLL Select
PLL_SyncOut O External PLL Synch Out signal
PLL_SyncExt I Select external synchronization mode
divRSTB I Reset Clock Divisor at Power up (Test only)
SDRAM Memory Interface
SdmData[63:0] I/O SDRAM Memory Data Bus
SdmCB[7:0] I/O SDRAM Memory Check bits for ECC
SdmDQM[7:0] O SDRAM Data Mask
SdmAddr[12:0] O SDRAM Address Bus