Toshiba TMPR7901, User Manual

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Chapter 9: DMA Controller
TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)
9-1
9. DMA Controller
The Direct Memory Access Controller (DMAC) employed in the TX7901 is a flexible direct
memory access engine that optimizes the data transfers between the C790 bus and the G-
Bus without significant intervention of the core CPU. Instead of having the CPU read data
from one source and write it to another, the DMA controllers can be programmed to
automatically transfer data independent of the CPU. This frees up the CPU and allows it to
continue executing other instructions simultaneous to the transfer of DMA data.
The following is a summary of the DMAC features in the TX7901:
•
Eight independent channels of direct memory access (DMA)
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Chaining via link lists of records
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Fixed/round-robin priority arbitration
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128-bit C790 bus support, capable of transferring 1.6/2.1 GB/second
•
Burst transfer of 1 to 8 quad-words on the C790 bus
•
Bi-endian support on the C790 bus
•
64-bit G-Bus support, capable of transferring 400/533 MB/second
•
32-/64-bit I/O device support on the G-Bus
•
Burst transfer of 1 to 8 quad-words on the G-Bus
•
Burst I/O support
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Block & slice support
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Memory byte alignment support on both the C790 bus and the G-Bus
•
FIFO queue size of 16 quad-words
Each DMA channel can move data from:
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C790 bus memory to C790 bus memory
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C790 bus memory to G-Bus I/O
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G-Bus I/O to C790 bus memory
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C790 bus memory to G-Bus memory
•
G-Bus memory to C790 bus memory
•
G-Bus memory to G-Bus memory