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Chapter 12: 10/100 IEEE802.3 Media Access Controller

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

12-14

12.3.1.4 Transmit Status Register (TSReg)

The Transmit Status register is updated after a frame is fully transmitted or the transmission
of a frame is aborted due to an error. The register can be read to determine if the frame was
successfully transmitted or to determine what errors occurred. Upon the completion of reset,
this register’s value is 0x0000_0000.

31

30

28 27

16

Tx

FBE

TxState[2:0]

0

1

3

12

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

TxFrm

Type

TxEx

Defer

Tx

Defer

Tx

SCol

Tx

MCol

Tx

ExCol

Tx

LCol

Tx

LCar

SQE

Tx

Und

HW

FDup

Sel

Tx

NoBuf

Tx

PStop

Tx

Good

1

2

1

1

1

1

1

1

1

1

1

1

1

1

1

Table 12-11 TSReg Register Field Descriptions

Bit(s)

Field

R/W

Description

31

TxFBE

R/W

Fatal Bus Error (0)

When set, indicates that a bus error occurred, and the MAC disables all of its bus access
operations.

30:28

TxState

[2:0]

R/W

Transmission Process State (000)

000 : Idle, TxEnable is 0

001 : Waiting, FIFO is empty or data is less than TxSOFTh (in TCReg)

010 : Waiting, Descriptor is not available

011 : Stopped, TxStart is reset to zero or Transmit Error occurred and TxEnHalt is set

100 : Suspended, Descriptor is not available

101 : Running, waiting for end of transmission

110 : Running, waiting for end of transmission and next Descriptor is not available

111 : Reserved

27:15

–

R/O

Reserved (0x000, 0)

14:13

TxFrmType

R/W

Transmit Frame Type (00)

00 Ethernet (RFC 894 encapsulation)

01 IEEE802.2 (RFC 1042 encapsulation)

10 VLAN I

11 VLAN II

12

TxExDefer

R/W

Excessive Deferral (0)

When set, indicates that the transmission was aborted because of an excessive deferral as
defined by the Defer bit in the transmit frame configuration register. This bit is not valid for full-
duplex.

11

TxDefer

R/W

Deferred (0)

When set, indicates the frame transmission was delayed because of a deferral. This bit is set
when a packet is transmitted with a collision and the standard back-off is selected in the
configuration register. This bit is not valid while the port is configured for full-duplex.

10

TxSCol

R/W

Single Collision (0)

When set, indicates that the packet being transmitted collided only once and was then
transmitted successfully on the Ethernet.

9

TxMCol

R/W

Multiple Collisions (0)

When set, indicates that the packet being transmitted collided more than once and was then
transmitted successfully on the Ethernet.

8

TxExCol

R/W

Collision Error (0)

When set, indicates that the packet transmission was aborted because of too many collisions.
The number of collision retries allowed is specified in the transmit frame configuration register.

7

TxLCol

R/W

Late Collision (0)

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Summary of Contents for TMPR7901

Page 1: ...TX System RISC TX79 Family TMPR7901 Symmetric 2 way superscalar 64 bit CPU ...

Page 2: ... are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications Also please keep in mind the precautions and conditions set forth in the Handling Guide for Semiconductor Devices or TOSHIBA Semiconductor Reliability Handbook etc The Toshiba products listed in this document are intended for usage in general electronics applications computer personal equipm...

Page 3: ...1 6 4 TWO STAGE DECODING PROCESS 6 1 6 4 1 Default Memory Map 6 6 6 4 2 Example connection of DIMMs 6 6 6 5 REGISTERS 6 7 6 5 1 Parameters register 6 9 6 5 2 Operation Mode Register 0x1E00_0040 R W 6 12 6 5 3 ECC Mode Register 0x1E00_0050 R W 6 15 6 5 4 ECC Error Status Register read only 0x1E00_0060 6 16 6 5 5 ECC Error Address Register read only 0x1E00_0070 6 17 6 5 6 Refresh Register 0x1E00_009...

Page 4: ...7 14 7 6 16 Interrupt Mask Register IRMSK 7 16 7 6 17 C790 Bus Latency Timer LT 7 16 7 6 18 NMI Status Register NRSTAT 7 17 7 6 19 G Bus Master Latency Timer 7 17 7 6 20 G Bus Broken Master Latency Timer 7 18 7 6 21 G Bus Slave Latency Timer 7 18 7 6 22 G Bus Retry Timer 7 19 7 6 23 GC Control Register 7 20 7 6 24 G Bus Status Register 7 21 7 6 25 G Bus Bad Address Register 7 22 7 6 26 G Bus Arbit...

Page 5: ...ation Register 8 38 8 7 6 Class Code Register 8 39 8 7 7 Cache Line Size Register 8 39 8 7 8 Master Latency Timer Register 8 40 8 7 9 Header Type 8 40 8 7 10 Subsystem Vendor ID 8 40 8 7 11 Subsystem ID Register 8 41 8 7 12 Interrupt Line Register 8 41 8 7 13 Interrupt Pin Register 8 41 8 7 14 MIN_GNT Register 8 42 8 7 15 MAX_LAT Register 8 42 8 7 16 TRDY Timeout Value 8 42 8 7 17 Retry Timeout Va...

Page 6: ...Status Registers TMTISR0 TMTISR1 TMTISR2 10 11 10 4 7 Fields for Timer Compare Registers A TMCPRAx and B TMCPRBx 10 13 10 4 8 Timer Read Registers TMTRR0 TMTRR1 TMTRR2 10 14 10 5 PROGRAMMABLE TIMER COUNTER OPERATION 10 14 10 5 1 Interval Timer Mode Operation 10 14 10 5 2 Pulse Generator Mode Operation 10 18 10 5 3 Watchdog Timer Mode Operation 10 20 10 5 4 Examples of Timer Counter Timing 10 21 CH...

Page 7: ...le Registers IER0 IER1 14 13 14 4 9 Modem Control Registers MCR0 MCR1 14 13 14 4 10 Modem Status Registers MSR0 MSR1 14 14 14 4 11 Scratch Registers SCR0 SCR1 14 15 14 4 12 Pre scalar Register 14 15 14 4 13 Divisor Latch LS and MS Registers DLL DLM 14 16 14 5 SPECIAL FEATURES 14 17 14 5 1 Transmit Machine Timing 14 17 14 5 2 THR Empty Interrupt Timing 14 17 14 5 3 FIFO Reset Timing 14 17 14 5 4 Rx...

Page 8: ...DCR 15 16 15 9 TSEI SYSTEM ERRORS 15 17 15 10 INTERRUPT GENERATION 15 17 15 10 1 Compatibility Mode 15 17 15 10 2 Toshiba Mode 15 18 15 10 3 Interrupt Generation on TSIC0 15 18 CHAPTER 16 CLOCKS 16 1 16 1 OVERVIEW 16 1 16 2 FEATURES 16 2 16 3 OPERATION 16 5 16 4 PERIPHERAL MODULE CLOCK 16 6 16 4 1 MAC Clock 16 6 16 4 2 UART Clock 16 6 16 4 3 SPI Clock 16 7 16 4 4 PCI Clock 16 7 16 4 5 Timer Clock ...

Page 9: ...NTATION 8 16 FIGURE 8 12 HIGH LEVEL ARCHITECTURE OF PCI CORE 8 33 FIGURE 8 13 PCI AND APPLICATION SIGNALS FOR PCI CORE 8 34 FIGURE 9 1 ROUND ROBIN PRIORITY SCHEME 9 3 FIGURE 9 2 DMA CHANNEL 5 9 5 FIGURE 9 3 C790 BUS OPERATIONS WITH CYCLE STEALING 9 5 FIGURE 9 4 C790 BUS OPERATIONS WITHOUT CYCLE STEALING 9 5 FIGURE 9 5 C790 BUS UNALIGNED ADDRESS CYCLE BREAK DOWN 9 7 FIGURE 9 6 DMAC OPERATION 9 8 FI...

Page 10: ...SEI BLOCK DIAGRAM 15 7 FIGURE 15 3 CPHA EQUALS 0 TRANSFER FORMAT 15 9 FIGURE 15 4 CPHA EQUALS 1 TRANSFER FORMAT 15 10 FIGURE 15 5 MCU INTERFACE SIGNALING 15 11 FIGURE 15 6 TSIC0 BEHAVIOR COMPATIBILITY MODE 15 19 FIGURE 16 1 TX7901 CLOCK DOMAIN DIAGRAM 16 3 FIGURE 16 2 TX7901 CLOCK DISTRIBUTION DIAGRAM 16 4 ...

Page 11: ...7 16 TABLE 7 19 C790 BUS LATENCY TIMER 7 16 TABLE 7 20 NMI STATUS REGISTER 7 17 TABLE 7 21 G BUS MASTER LATENCY TIMER 7 17 TABLE 7 22 G BUS BROKEN MASTER LATENCY TIMER 7 18 TABLE 7 23 G BUS SLAVE LATENCY TIMER 7 18 TABLE 7 24 G BRIDGE RETRY TIMER FIELDS 7 19 TABLE 7 25 THE GC CONTROL REGISTER FIELDS 7 20 TABLE 7 26 G BRIDGE STATUS REGISTER FIELDS 7 21 TABLE 7 27 C790 BUS STATUS REGISTER FIELDS 7 2...

Page 12: ...TE COUNT REGISTER FIELD DEFINITIONS 9 15 TABLE 9 8 NEXT RECORD POINTER REGISTER FIELD DEFINITIONS 9 16 TABLE 9 9 GLOBAL CONTROL AND STATUS REGISTER FIELD DESCRIPTIONS 9 16 TABLE 9 10 C790 BUS ERROR ADDRESS REGISTER FIELD DESCRIPTIONS 9 17 TABLE 9 11 G BUS ERROR ADDRESS REGISTER FIELD DESCRIPTIONS 9 18 TABLE 10 1 TIMER MODES AND CHANNELS 10 1 TABLE 10 2 TX7901 PROGRAMMABLE TIMER COUNTER SIGNALS 10 ...

Page 13: ...LUES FOR 100 MB AND 10 MB 12 27 TABLE 12 31 MIIM CONTROL REGISTER FIELD DESCRIPTIONS 12 33 TABLE 12 32 MIIM DATA REGISTER FIELD DESCRIPTIONS 12 34 TABLE 12 33 PERFECT TABLE FIELD DESCRIPTIONS 12 35 TABLE 12 34 RECEIVE DESCRIPTOR FIELD DESCRIPTIONS 12 38 TABLE 12 35 TRANSMIT DESCRIPTOR FIELD DESCRIPTIONS 12 40 TABLE 14 1 SERIAL I O SIGNAL DESCRIPTIONS 14 3 TABLE 14 2 DEVICE REGISTER ADDRESSING FOR ...

Page 14: ...Handling Precautions ...

Page 15: ......

Page 16: ... It is the responsibility of the buyer when utilizing TOSHIBA products to observe standards of safety and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life bodily injury or damage to property In developing your designs please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products speci...

Page 17: ...1 Using Toshiba Semiconductors Safely 1 2 ...

Page 18: ...els Explanation of labels Explanation of labels Explanation of labels Indicates an imminently hazardous situation which will result in death or serious injury if you do not follow instructions Indicates a potentially hazardous situation which could result in death or serious injury if you do not follow instructions Indicates a potentially hazardous situation which if not avoided may result in mino...

Page 19: ... a device is on do not touch the device s heat sink Heat sinks become hot so you may burn your hand Do not touch the tips of device leads Because some types of device have leads with pointed tips you may prick your finger When conducting any kind of evaluation inspection or testing be sure to connect the testing equipment s electrodes or probes to the pins of the device under test before powering ...

Page 20: ...t circuit current will flow continuously and the device may break down or burst into flames resulting in fire or injury When incorporating a visible semiconductor laser into a design use the device s internal photodetector or a separate photodetector to stabilize the laser s radiant power so as to ensure that laser beams exceeding the laser s rated radiant power cannot be emitted If this stabilizi...

Page 21: ...ember to take the device s forward and reverse losses into account The leakage current in these devices is greater than that in ordinary rectifiers as a result if a high speed rectifier is used in an extreme environment e g at high temperature or high voltage its reverse loss may increase causing thermal runaway to occur This may in turn cause the device to explode and scatter shrapnel resulting i...

Page 22: ...ls in the working area are grounded to earth Place a conductive mat over the floor of the work area or take other appropriate measures so that the floor surface is protected against static electricity and is grounded to earth The surface resistivity should be 104 to 108 Ω sq and the resistance between surface and ground 7 5 105 to 108 Ω Cover the workbench surface also with a conductive mat with a...

Page 23: ...rs boxes jigs or bags that are made of anti static materials or materials which dissipate electrostatic charge Make sure that cart surfaces which come into contact with device packaging are made of materials which will conduct static electricity and verify that they are grounded to the floor surface via a grounding chain In any location where the level of static electricity is to be closely contro...

Page 24: ...es and packaging materials with care To avoid damage to devices do not toss or drop packages Ensure that devices are not subjected to mechanical vibration or shock during transportation Ceramic package devices and devices in canister type packages which have empty space inside them are subject to damage from vibration and shock because the bonding wires are secured only at their ends Plastic molde...

Page 25: ... If devices have been stored for more than two years their electrical characteristics should be tested and their leads should be tested for ease of soldering before they are used 3 2 2 Moisture proof packing Moisture proof packing should be handled with care The handling procedure specified for each packing type should be followed scrupulously If the proper procedures are not followed the quality ...

Page 26: ...mperature which it can withstand bake at 125 C for 20 hours Some devices require a different procedure Tube Transfer devices to trays bearing the Heatproof marking or indicating the temperature which they can withstand or to aluminum tubes before baking at 125 C for 20 hours Tape Deviced packed on tape cannot be baked and must be used within the effective usage period after unpacking as specified ...

Page 27: ... each pin the allowable power dissipation and the junction and storage temperatures If the voltage or current on any pin exceeds the absolute maximum rating the device s internal circuitry can become degraded In the worst case heat generated in internal circuitry can fuse wiring or cause the semiconductor chip to break down If storage or operating temperatures exceed rated values the package seal ...

Page 28: ...chip into a breakdown condition Once the chip falls into the latch up state even though the excess voltage may have been applied only for an instant the large current continues to flow between Vcc Vdd and GND Vss This causes the device to heat up and in extreme cases to emit gas fumes as well To avoid this problem observe the following precautions 1 Do not allow voltage levels on the input and out...

Page 29: ... θca Tc Ta P in which θja thermal resistance between junction and surrounding air C W θjc thermal resistance between junction and package surface or internal thermal resistance C W θca thermal resistance between package surface and surrounding air or external thermal resistance C W Tj junction temperature or chip temperature C Tc package surface temperature or case temperature C Ta ambient tempera...

Page 30: ...ulnerable to induced noise or surges from outside sources Consequently malfunctions or breakdowns can result from overcurrent or overvoltage depending on the types of device used To protect against noise lower the impedance of the pattern line or insert a noise canceling circuit Protective measures must also be taken against surges For details of the appropriate protective measures for a particula...

Page 31: ...rds Each country has safety standards which must be observed These safety standards include requirements for quality assurance systems and design of device insulation Such requirements must be fully taken into account to ensure that your design conforms to the applicable safety standards 3 3 15 Other precautions 1 When designing a system be sure to incorporate fail safe and other appropriate measu...

Page 32: ... are essentially two main types of semiconductor device package lead insertion and surface mount During mounting on printed circuit boards devices can become contaminated by flux or damaged by thermal stress from the soldering process With surface mount devices in particular the most significant problem is thermal stress from solder reflow when the entire package is subjected to heat This section ...

Page 33: ...package type 3 5 2 Socket mounting 1 When socket mounting devices on a printed circuit board use sockets which match the inserted device s package 2 Use sockets whose contacts have the appropriate contact pressure If the contact pressure is insufficient the socket may not make a perfect contact when the device is repeatedly inserted and removed if the pressure is excessively high the device leads ...

Page 34: ...e temperature of between 210 C and 240 C Refer to Figure 4 for an example of a good temperature profile for infrared or hot air reflow 210 30 s or less Time s 60 120 s C 240 160 140 Package surface temperature Figure 4 Sample temperature profile for infrared or hot air reflow 3 Using hot air reflow Complete hot air reflow within 30 seconds at a package surface temperature of between 210 C and 240 ...

Page 35: ...leaning agent Doing so can rub off the markings 4 The dip cleaning shower cleaning and steam cleaning processes all involve the chemical action of a solvent Use only recommended solvents for these cleaning methods When immersing devices in a solvent or steam bath make sure that the temperature of the liquid is 50 C or below and that the circuit board is removed from the bath within one minute 5 Ul...

Page 36: ...re have their reverse side exposed To ensure that the chip will not be cracked during mounting ensure that no mechanical shock is applied to the reverse side of the chip Electrical contact may also cause a chip to fail Therefore when mounting devices make sure that nothing comes into electrical contact with the reverse side of the chip If your design requires connecting the reverse side of the chi...

Page 37: ...apply the coating thinly and evenly do not use too much Also be sure to use a non volatile compound as volatile compounds can crack after a time causing the heat radiation properties of the heat sink to deteriorate 5 If the device is housed in a plastic package use caution when selecting the type of silicone compound to be applied between the heat sink and the device With some types the base oil s...

Page 38: ...can damage a device due to the occurrence of electrostatic discharge Unless damp proofing measures have been specifically taken use devices only in environments with appropriate ambient moisture levels i e within a relative humidity range of 40 to 60 3 6 3 Corrosive gases Corrosive gases can cause chemical reactions in devices degrading device characteristics For example sulphur bearing corrosive ...

Page 39: ...in devices which will adversely affect a device s electrical characteristics To avoid this problem do not use devices in dusty or oily environments This is especially important for optical devices because dust and oil can affect a device s optical characteristics as well as its physical integrity and the electrical performance factors mentioned above 3 6 8 Fire Semiconductor devices are combustibl...

Page 40: ...se with Toshiba products in microcontroller oscillator applications are listed in Toshiba databooks along with information about oscillation conditions If you use a resonator not included in this list please consult Toshiba or the resonator manufacturer concerning the suitability of the device for your application 2 Undefined functions In some microcontrollers certain instruction code values do no...

Page 41: ...4 Precautions and Usage Considerations 4 2 ...

Page 42: ...TX7901 User s Manual Rev 6 30T November 2001 DOCUMENT NUMBER M 99 00004 07 ...

Page 43: ......

Page 44: ...ncept This class of product is targeted for applications that require a high performance cost effective solution such as networking printers and set top boxes 1 2 Terminology 1 2 1 Abbreviations used 802 3x IEEE 802 3x standard for Ethernet based Local Area Networks b bits e g 1 Mb 1 Mega bit B Bytes e g 4 MB 4 Mega Bytes Suffix for active low signals BIU Bus Interface Unit BTAC Branch Target Addr...

Page 45: ...implementations from multiple vendors intended to be incorporated into a larger IC design ISA Instruction Set Architecture ITLB Instruction Translation Look aside Buffer JTLB Joint Translation Look aside Buffer MAC Multiply Accumulator CPU such as iMAC integer MAC fMAC floating point MAC Media Access Controller Ethernet controller such as eMAC MBPS Million s of bits per second MII Media Independen...

Page 46: ...exadecimal numbers and are prefixed by the characters 0x which are not part of the number in keeping with Verilog and C Language Terminology In order to improve legibility the underscore character _ separates numbers larger than four hex digits in length into four digit groups Internal signals start with a lower case module name followed by suffixes with capitalized initial letter s Active Low int...

Page 47: ...che write back cache WBB non blocking load and data cache Pre fetch instruction to enhance performance 64 entry fully associative branch target address cache 48 entry fully associative JTLB supporting 4 KB 16 MB page size WinCE profile II recommended IEEE754 Double Precision FPU tightly coupled with the CPU core FPU is compatible with the TX49 Bi endian Little Endian and Big Endian operations supp...

Page 48: ... Write operations The SDRAMC supports 1 GB memory with four DIMMs 8M 8B 4 or two double side DIMMs 8M 8B 4 2 PC 100 133 DIMM SO DIMM Internal PLL for de skewing clock and data between the TX7901 and SDRAM DIMMs Four bank interleaving for 64 128 256 Mb SDRAMs Two bank interleaving for 16 Mb SDRAMs ECC single bit error correction double bit error detection Aligned burst transactions DMA Controller D...

Page 49: ...their own particular 24 bit up counter and control registers for implementing each timer control channel Timer 0 is an internal timer that uses the internal clock and operates in the Internal Timer Mode which causes periodic interrupts Timer 1 for Channel 1 operates in the Interval Timer Mode or Pulse Generator Mode which generates waveforms of arbitrary frequencies and duty ratios Timer 2 for Cha...

Page 50: ...ing is the block diagram of the TX7901 Figure 3 1 TX7901 Block Diagram C790 Bus 128 bit Internal System Bus BIU PCU LSU PLL IU C790 I 32K IFU D 32K SPI Serial Boot ROM Test Logic SDRAM Controller DMAC Timers INTC 64 Bit G Bus Bridge 64 bit Internal G Bus DEBUG FPU Dual UARTs Dual MACs PCI Bridge ...

Page 51: ...2 internal and external sources of interrupts and interrupt controller for these interrupt sources Timers 3 channel 24 bit up counters work as the interval timer pulse generator and watchdog timer UART 2 channel serial I Os NS 16550 software compatible Channel 0 has full function Channel 1 has two pins SW SOUT only and is used for the debug monitor SPI Serial Peripheral Interface connects the seri...

Page 52: ...I Dual MACs Test Logic SDRAMC DMAC INTC Serial ROM Flash ROM RTC SDRAM Memory Devices PC100 133 DIMM PCI Controller 1 e g USB i f PCI Controller 2 e g EIDE PCI Controller 3 e g IEEE1394 Timers CDROM HDD etc MODEMS PHY Dial Up Lines DEBUG FPU 200 266 MHz 128b 100 MHz 133 MHz 64b 50 MHz 66 MHz Note 266 MHz CPU and PC 133 SDRAM interfaces are being planned as premium products PCI Bridge ...

Page 53: ...01 User s Manual Rev 6 30T Nov 2001 3 4 3 1 Reset Configuration C790 Pins define the endianness SPI 2 MHz 133 1 56 MHz 100 of the bit rate accesses Boot ROM SDRAM 8 MB per DIMM chip select starting at physical address 0x0000_0000 ...

Page 54: ... TX7901 virtual and physical addresses are both 32 bits wide Figure 4 1 Memory Map 0xFFFF_FFFF 0x2100_0000 0x1F00_0000 0x1E00_1000 0x1E00_0000 0x0000_0000 CGUPAn CGLPAn CGUPAm CGLPAm UROMA LROMA UIRA LIRA GCUIRA GCLIRA CGUMAn CGLMAn CGUMAn CGLMAn ROM Registers SDRAM Memory ROM Memory Window Memory Window SPI 0x1FC0_FFFF 0x1FC0_0000 MAC DMA C790 Bus G Bus PCI PCI Memory PCI Memory PCI Memory PCI Me...

Page 55: ...o the chapters on the SDRAM memory controller and PCI controller 4 2 Register Map The following is the register map of the TX7901 built in modules 0x1E00_0000 0x1E00_0FFF SDRAM Memory Controller on the C790 Bus 0x1E00_1000 0x1E00_1FFF DMA Controller 0x1E00_2000 0x1E00_2FFF G Bus Bridge and Interrupt Controller 0x1E00_3000 0x1E00_3FFF PCI Bridge PGB 0x1E00_4000 0x1E00_4FFF Timer Counter 0x1E00_5000...

Page 56: ...R W 128 D3HIGH DIMM 3 HIGH Address Decode 0x1E00_0170 R W 128 DMA Controller Base Address 0x1E00_1000 CCR0 Channel 0 Control Register 0x1E00_1000 R W 64 CSR0 Channel 0 Status Register 0x1E00_1010 R W 64 SAR0 Channel 0 Source Address Register 0x1E00_1020 R W 64 DAR0 Channel 0 Destination Address Register 0x1E00_1030 R W 64 BCR0 Channel 0 Byte Count Register 0x1E00_1040 R W 64 NRPR0 Channel 0 Next R...

Page 57: ...el 6 Byte Count Register 0x1E00_1640 R W 64 NRPR6 Channel 6 Next Record Pointer Register 0x1E00_1650 R W 64 RESERVED 0x1E00_1660 0x1E00_16F0 CCR7 Channel 7 Control Register 0x1E00_1700 R W 64 CSR7 Channel 7 Status Register 0x1E00_1710 R W 64 SAR7 Channel 7 Source Address Register 0x1E00_1720 R W 64 DAR7 Channel 7 Destination Address Register 0x1E00_1730 R W 64 BCR7 Channel 7 Byte Count Register 0x...

Page 58: ...128 R W 64 GBBAR G Bus Bad Address Register 0x1E00_2130 R 64 GBARSR G Bus Arbiter Request Status Register 0x1E00_2138 R 64 GBAGSR G Bus Arbiter Granted Status Register 0x1E00_2140 R 64 GBAMSR G Bus Arbiter Master Status Register 0x1E00_2148 R W 64 GBACR G Bus Arbiter Control Register 0x1E00_2150 R W 64 PCI G Bus Bridge PCI Controller Base Address 0x1E00_3000 Device Vendor ID Register 0x1E00_3000 R...

Page 59: ...0_3180 R W 64 p2gBase3 p2gwindow Base Address Register 3 0x1E00_3188 R W 64 Ia Failing Transaction Address Register 0x1E00_3190 R W 64 Reserved 0x1E00_3198 0x1E00_3FFF Programmable Timer Counters Base Address 0x1E00_4000 TMTCR0 Timer Control Register 0 0x1E00_4000 R W 32 TMTISR0 Timer Interrupt Status Register 0 0x1E00_4004 R W 32 TMCPRA0 Compare Register A 0 0x1E00_4008 R W 32 TMCPRB0 Compare Reg...

Page 60: ...rrent Descriptor Pointer 0x1E00_5090 R 32 RCDReg Receive Frame Current Descriptor Pointer 0x1E00_5098 R 32 Reserved 0x1E00_50A0 0x1E00_50FF peMACC0 Internal Test Register 0 peMACC 0x1E00_5100 R W 64 peMACT0 Internal Test Register 0 peMACT 0x1E00_5108 R W 64 IPGReg0 Back to Back IPG gap0 0x1E00_5110 R W 64 NBTBReg0 Non Back to Back IPG gap0 0x1E00_5118 R W 64 peCLRT0 Internal Test Register0 peCLRT ...

Page 61: ...ved 0x1E00_5310 R W 64 UFCnt0 Undersized Frames 0x1E00_5318 R W 64 FFCnt0 Fragmented Frames 0x1E00_5320 R W 64 JFRCnt0 Jabber Frames Received 0x1E00_5328 R W 64 NRDMFCnt0 No RxDescriptor Missed Frames 0x1E00_5330 R W 64 NRMFCnt0 No RxFIFO Missed Frames 0x1E00_5338 R W 64 MIIMCR0 MIIM Control Register 0x1E00_5400 R W 64 MIIMDR0 MIIM Data Register 0x1E00_5408 R W 64 PhyAddr0_0 Physical Address 0 0x1...

Page 62: ...E00_61A8 R W 64 LSAI1 Local Station Addr I 0x1E00_61B0 R W 64 peVLTP1 Internal Test Register peVLTP 0x1E00_61C8 R W 64 TBTCnt1 Total Bytes Transmitted Count Register 0x1E00_6200 R W 64 TGFTCnt1 Total Good Frames Transmitted 0x1E00_6208 R W 64 MFTCnt1 Multicast Frames Transmitted 0x1E00_6210 R W 64 BFTCnt1 Broadcast Frames Transmitted 0x1E00_6218 R W 64 TxFrame64_1 Frames Transmitted TxFrame64 0x1E...

Page 63: ...R W 64 PhyAddr4_1 Physical Address 4 0x1E00_6620 R W 64 PhyAddr5_1 Physical Address 5 0x1E00_6628 R W 64 PhyAddr6_1 Physical Address 6 0x1E00_6630 R W 64 PhyAddr7_1 Physical Address 7 0x1E00_6638 R W 64 PhyAddr8_1 Physical Address 8 0x1E00_6640 R W 64 PhyAddr9_1 Physical Address 9 0x1E00_6648 R W 64 PhyAddrA_1 Physical Address A 0x1E00_6650 R W 64 PhyAddrB_1 Physical Address B 0x1E00_6658 R W 64 P...

Page 64: ... R W 8 PGB1 Optional Base Address 0x1E00_A000 Device Vendor ID Register 0x1E00_A000 R 32 Status Command Register 0x1E00_A004 R W 32 Class Code Revision ID Register 0x1E00_A008 R 32 BIST Header Type Master Latency Timer Cache line Size 0x1E00_A00C R W 32 Memory Base Address 0 0x1E00_A010 R W 32 Memory DAC Base Address 0 0x1E00_A014 R W 32 Memory Base Address 1 0x1E00_A018 R W 32 Memory DAC Base Add...

Page 65: ...0x1E00_A138 R W 64 g2pUpper3 g2pwindow Upper Address Register 3 0x1E00_A140 R W 64 g2pBase0 g2pwindow Base Address Register 0 0x1E00_A148 R W 64 g2pBase1 g2pwindow Base Address Register 1 0x1E00_A150 R W 64 g2pBase2 g2pwindow Base Address Register 2 0x1E00_A158 R W 64 g2pBase3 g2pwindow Base Address Register 3 0x1E00_A160 R W 64 g2pCycleType g2pwindow Cycle Type Register 0x1E00_A168 R W 64 p2gBase...

Page 66: ...I compatible ISA with selected MIPS IV ISA Pre fetch and Move Conditional Instruction Additional multimedia instruction set support to provide SIMD operation 32 KB 2 way set associative Instruction Cache and 32 KB 2 way set associative Data Cache Supports the data cache line lock write back cache and non blocking load functions and the prefetch instruction 64 entry fully associative branch target ...

Page 67: ...che Tag BHT Predecode Inst RAMs 32kB 2 way set assoc Issue Logical Staging Resigters 2 Issue In order GPR 32x128 bit wide registers Operand Bypass Logic Instruction Virtual Address IVA MMU JTLB DTLB 4 entries Virtual Address Computation Logic FPR 32x64 bit wide registers UCAB Data Cache D Cache 32 KB 2 way set assoc Data Virtual Address DVA WBB Response Buffer Bus Interface Unit Result and Move Bu...

Page 68: ...64 bit data paths share a single 128 bit multimedia shifter during 128 bit wide shift operations Load Store LS Pipe The Load Store LS pipe supports a single issue of Load and Store instructions at widths ranging from one byte 8 bits to one quad word 128 bits Memory Management Unit MMU The Memory Management Unit supports the address translation functions of the C790 It contains a 48 entry fully ass...

Page 69: ... and divide instructions 5 4 FPU Registers The floating point unit COP1 has thirty two 64 bit wide floating point registers It also contains two floating point control registers 5 5 Memory Management The C790 provides a memory management unit MMU which uses an on chip translation look aside buffer TLB to translate virtual addresses into physical addresses Features MIPS III compatible 32 bit MMU Op...

Page 70: ...nt unit tightly coupled to the C790 Supports double precision and single precision formats as defined in the IEEE 754 specifications Compatible with the TX49 FPU No hardware support for denormalized numbers 5 8 Performance Monitor The performance monitor provides the means for gathering statistical information about the internal events of the C790 and its pipeline during program execution The stat...

Page 71: ...MIPS ISA Features One Instruction Address Breakpoint register One Instruction Address Breakpoint Mask register One Data Address Breakpoint register One Data Address Breakpoint Mask register One Data Value Breakpoint register One Data Value Breakpoint Mask register Each breakpoint is individually enabled Breakpoint function can be selectively enabled in User Supervisor Kernel and Exception modes Ex...

Page 72: ...gned 8 quad word burst transfers 6 3 Address Space Decoding The SDRAM Controller has a fully programmable address map It uses a two stage decoding process where major device regions are decoded first and then the individual devices are sub decoded Addresses for regions in 256 MB units are compared by exact matching and individual device addresses are compared by size comparison One device DIMM the...

Page 73: ...ip select signal is activated Any device region can be disabled by setting the value of the LOW decoder to be higher than that of the HIGH decoder The LOW and HIGH Decode Registers cannot be programmed in the region from 0x_1E00_0000 to 0x_20FF_FFFF This is reserved for TX7901 registers and Boot Devices It is important to note that devices never span across region boundaries This is detected by re...

Page 74: ...the HIGH register again after LOW and HIGH are written If the HIGH register is read the same as it was written then it is okay If it is different because the HIGH region field is the same as that of LOW then it is okay to place a DIMM across the 256 MB region boundary la r4 LOW of DIMM0 la r5 HIGH of DIMM1 la r7 SDRAM base address sq r4 D0LOW r7 sq r5 D0HIGH r7 lq r6 D0HIGH r7 bne r5 r6 crossing D...

Page 75: ... 2001 6 4 Figure 6 3 Example Connection of Single sided DIMMs DIMM0 DIMM1 DIMM2 DIMM3 BankAddr 1 0 Address 12 0 RAS CAS WE sdmCSB 0 sdmCSB 1 sdmCSB 2 sdmCSB 3 data 63 0 check bits 7 0 DQM 7 0 RefClk TX7901 100 133 MHz Clock Distribution 18 72b 8b 8b 8b 8b 8b 8b 8b 8b 8b ...

Page 76: ... Nov 2001 6 5 Figure 6 4 Example Connection of Double sided DIMMs DIMM0 2 DIMM1 3 BankAddr 1 0 Address 12 0 RAS CAS WE sdmCSB 0 sdmCSB 1 sdmCSB 2 sdmCSB 3 data 63 0 check bits 7 0 DQM 7 0 RefClk TX7901 18 72b 8b 8b 8b 8b 8b 8b 8b 8b 8b 100 133 MHz Clock Distribution ...

Page 77: ...hows an example of four 64 MB DIMMs Table 6 2 Example Values for Four DIMMs Device CS LOW HIGH Initial Size DIMM0 sdrCSB 0 D0LOW 0x0 000_ 0000 D0HIGH 0x0 3FF_FFFF 64 MB DIMM1 sdrCSB 1 D1LOW 0x0 400_0000 D1HIGH 0x0 7FF_FFFF 64 MB DIMM2 sdrCSB 2 D2LOW 0x0 800_0000 D2HIGH 0x0 BFF_FFFF 64 MB DIMM3 sdrCSB 3 D3LOW 0x0 C00_0000 D3HIGH 0x0 FFF_FFFF 64 MB 6 4 2 Example connection of DIMMs It is possible to...

Page 78: ...egister 0x1E00_0040 R W 128 DEMR ECC Mode Register 0x1E00_0050 R W 128 DEESR ECC Error Status Register 0x1E00_0060 R 128 DEEAR ECC Error Address Register 0x1E00_0070 R 128 RESERVED 0x1E00_0080 DREFRESH Refresh Register 0x1E00_0090 R W 128 DDRIVE SDRAM Interface Output Drive Strength Control Register 0x1E00_00A0 R W 128 D0LOW DIMM 0 LOW Address Decode 0x1E00_0100 R W 128 D0HIGH DIMM 0 HIGH Address ...

Page 79: ... 6 30T Nov 2001 6 8 Figure 6 5 SDRAM Registers D0PR D0LOW D0HIGH D1PR D1LOW D1HIGH D2PR D2LOW D2HIGH D3PR D3LOW D3HIGH sdmCSB 0 sdmCSB 1 sdmCSB 2 sdmCSB 3 DIMM0 DIMM1 DIMM2 DIMM3 DEMR DEESR DEEAR ECC DOMR General Control Physical Address SDRAMC DREFRESH DDRIVE ...

Page 80: ...ion Timing Symbol DSL 1 0 Device Select 01 00 16 Mb SDRAM 01 64 128 Mb SDRAM 10 256 Mb SDRAM 11 Reserved 15 2 Reserved CAS 17 16 CAS Latency 11 These bits specify the timing for the first read data after SDRAM samples a column address 00 01 Reserved 10 2 clock cycles 11 3 clock cycles tCAS A2RWI 20 18 Active to Read Write Interval 011 Specifies the earliest timing for a READ WRITE command after an...

Page 81: ...tRFC A2P 29 Activate to Precharge 1 This bit specifies the earliest timing for a PRECHARGE command after an ACTIVE command 0 5 clock cycles 1 6 clock cycles tRAS 31 30 Reserved The following figure shows example timing parameters Figure 6 6 Example Timing Parameters T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 tRAS ACTIVE READ PRE tCAS ROW COL Read data Read data ACTIVE WRITE Any command tRCD tRAS ROW COL tW...

Page 82: ... Device Select 01 00 16 Mb SDRAM 01 64 128 Mb SDRAM 10 256 Mb SDRAM 11 Reserved 31 2 Reserved Other parameters use the same values as DIMM 0 DIMM 2 Parameters Register 0x1E00_0020 R W 127 32 0 96 31 2 1 0 0 D S L 30 2 Field Bit Description DSL 1 0 Device Select 01 00 16 Mb SDRAM 01 64 128 Mb SDRAM 10 256 Mb SDRAM 11 Reserved 31 2 Reserved Other parameters use the same values as DIMM 0 ...

Page 83: ... T A T 0 O P M 19 3 7 3 This register is used to execute commands other than standard memory reads and writes to the SDRAM Bits 12 10 are used to check the current state of the SDRAM Controller Field Bit s Description OPM 2 0 Operation Mode 001 000 Normal SDRAM Mode Read Write 001 NOP Commands 010 Precharge All Banks 011 Writing to the SDRAM Mode Register Each DIMM could have a different Mode 100 ...

Page 84: ...he Precharge All Banks command is used to deactivate the open row The Precharge All Banks command is the first command called after reset In this mode any write to a particular DIMM causes the Precharge command to be issued Once a bank has been precharged it is in the idle state and must be activated prior to any read or write commands being issued to that bank This sequence will be performed by t...

Page 85: ...refresh counter internal to the SDRAM chip At least eight Auto Refresh commands are required for the power on sequence 6 5 2 6 Initialization sequence Intel s PC SDRAM Specification Rev 1 7 November 1999 recommends the sequence described below Following the initialization sequence the device must be ready for full functionality SDRAM devices are initialized by the following sequence 1 At least one...

Page 86: ...ng memory writes and error detection only during memory reads 010 ECC Enable Mode Performs check bit generation during memory writes and error detection and correction during memory reads 011 Diagnostic Mode for verifying the ECC function All check bits are forced to check bits in this register during memory writes SEIE 3 3 Single ECC Error Interrupt Enable 0 MEIE 4 4 Multiple ECC Error Interrupt ...

Page 87: ...d an interrupt is generated After an ECC Error the ECC Error Status Register and the ECC Error Address Register keep the status and address of the latest error until it has been read SBE and MBE are cleared after it is read Regardless of the ECC Interrupt Enable Bit in the ECC Mode Register these registers are updated when an ECC error is detected Field Bit s Description SBE 0 Single Bit Error SBE...

Page 88: ...0x0400 Implements standard CAS before refreshing RAS Refresh rates for all banks can be programmed in this register RefIntCnt is a 14 bit counter If the default value is 0x400 for example and if the clock is 100 MHz then a refresh sequence will occur every 10 µs 10 ns 1024 10 24 µs 15 14 Reserved 0 NSRF 16 Non Staggered Refresh 0 In the non staggered refresh mode this bit is set and sdrCSB 3 0 wil...

Page 89: ...0 output drive strength Field Bits Description CADSL 1 0 Control Address output drive strength select 11 00 8 mA 01 16 mA 10 24 mA 11 32 mA 2 3 Reserved 0 DMDSL 5 4 Data Data mask output drive strength select 10 00 8 mA 01 16 mA 10 24 mA 11 32 mA 31 6 Reserved Note Currently 16 mA fixed drivers are implemented for Data Data mask output due to I O area limitation DMDSL doesn t affect drive strength...

Page 90: ...31 28 R O DIMM 0 27 20 R W HIGH Boundary 19 0 R O 1 6 5 10 DIMM 1 LOW Address Decode 0x1E00_0120 127 32 0 96 31 28 27 20 19 0 DIMM 1 LOW boundary 0 0 4 R W 8 20 Bits R W Description 31 28 R W DIMM1 27 20 R W LOW boundary 19 0 R O 0 6 5 11 DIMM1 HIGH Address Decode 0x1E00_0130 127 32 0 96 31 28 27 20 19 0 DIMM1 HIGH boundary 1 1 4 R O 8 20 Bits R W Description 31 28 R O DIMM1 27 20 R W HIGH Boundar...

Page 91: ...ller TX7901 User s Manual Rev 6 30T Nov 2001 6 20 6 5 12 DIMM 2 LOW Address Decode 0x1E00_0140 127 32 0 96 31 28 27 20 19 0 DIMM 2 LOW boundary 0 0 4 R W 8 20 Bits R W Description 31 28 R W DIMM 2 27 20 R W LOW boundary 19 0 R O 0 ...

Page 92: ...1 28 R O DIMM 2 27 20 R W HIGH Boundary 19 0 R O 1 6 5 14 DIMM 3 LOW Address Decode 0x1E00_0160 127 32 0 96 31 28 27 20 19 0 DIMM 3 LOW boundary 0 0 4 R W 8 20 Bits R W Description 31 28 R W DIMM 3 27 20 R W LOW boundary 19 0 R O 0 6 5 15 DIMM 3 HIGH Address Decode 0x1E00_0170 127 32 0 96 31 28 27 20 19 0 DIMM 3 HIGH boundary 1 1 4 R O 8 20 Bits R W Description 31 28 R O DIMM3 27 20 R W HIGH Bound...

Page 93: ...ess CA 12 0 12 11 10 9 8 7 6 3 2 0 16 Mb 6 22 12 7 23 11 8 5 3 64 Mb 128 Mb 7 6 7 6 24 22 12 24 22 12 AP 25 23 11 8 5 3 AP 26 25 23 11 8 5 3 256 Mb 7 6 27 24 22 12 AP 26 25 23 11 8 5 3 No pins in this device Don t care AP Auto Precharge Assign a constant of 1 to this bit Number bit number of sysPAddr 27 3 Address range Device size sysPAddr System elements 31 28 27 26 25 24 23 12 11 6 5 4 3 2 1 0 2...

Page 94: ...umber of 1s in the generated syndrome for each data bit in an error The SDRAM Controller supports ECC detection and correction of 64 bit 72 bit SDRAMs If ECC is enabled and there is an ECC error in the read an interrupt will be asserted to the CPU and the ECC Error Status Register will be set to indicate that bad data were returned For 64 bit 72 bit SDRAMS if ECC is enabled check bits will be gene...

Page 95: ...Transaction by the SDRAM Controller 1 READ All Data and Check Bits 2 Modify Check Byte in TX7901 3 Write New Data and Modified Check Byte x72 SDRAM x8 SDRAM 1 x8 SDRAM 2 x8 SDRAM 7 x8 SDRAM 8 x8 SDRAM 9 y y y Data 7 0 Data 15 8 Data 55 48 Data 63 56 CB 7 0 SDQM 0 ASSERTED SDQM 1 ASSERTED SDQM 6 ASSERTED SDQM 7 ASSERTED SDQM X ASSERTED x72 SDRAM x8 SDRAM 1 x8 SDRAM 2 x8 SDRAM 7 x8 SDRAM 8 x8 SDRAM ...

Page 96: ...0a0 Output Driver Strength define D0LOW 0x0100 DIMM0 LOW address define D0HIGH 0x0110 DIMM0 HIGH address define D1LOW 0x0120 DIMM1 LOW address define D1HIGH 0x0130 DIMM1 HIGH address define D2LOW 0x0140 DIMM2 LOW address define D2HIGH 0x0150 DIMM2 HIGH address define D3LOW 0x0160 DIMM3 LOW address define D3HIGH 0x0170 DIMM3 HIGH address configuration for single 32MB DIMM on DIMM0 consist of five 6...

Page 97: ...R k1 set up SDRAM address windows li t0 RAMBASE start address of DIMM0 li t2 RAMBASE RAM 32MB 1 end address of DIMM0 sq t0 D0LOW k1 store DIMM0 LOW reg starting 0x0000_0000 sq t2 D0HIGH k1 store DIMM0 HIGH reg 32MB li t0 RAMBASE RAM32MB li t2 RAMBASE RAM32MB 2 1 sq t0 D1LOW k1 store DIMM1 LOW reg starting 0x0200_0000 sq t2 D1HIGH k1 store DIMM1 HIGH reg 0MB li t0 RAMBASE RAM32MB 2 li t2 RAMBASE RA...

Page 98: ... Register la t2 SDRM_CL3 sw 0 0 t2 write address goes to MODE register lw t0 DOMR k1 read DOMR to make sure Write Mode Reg It takes more than 2 x sysBusClk start Refresh li t0 SDR_RFSH sq t0 DREFRESH k1 return to Normal mode of SDRAMC access li t0 DOMR_NORMAL sq t0 DOMR k1 sync l lw t0 DOMR k1 read DOMR to make sure Normal mode sync l Now SDRAM is ready for access ...

Page 99: ... devices on the G Bus and G Bus Mastering devices access to the main memory on the C790 Bus Figure 7 1 shows the block diagram of the G bridge Figure 7 1 C790 Bus G Bus Bridge Block Diagram C790 Bus G Bus G Bus Master State Machine CGFIFO 8x1QW GCFIFO 9x1QW C790 Bus Receiver Interface C790 Bus Transmitter Interface G Bus Transmit Interface G Bus Receiver Interface C790 Bus Slave State Machine C790...

Page 100: ...the C790 initiates a bus cycle to a G Bus device the bridge detects the address and posts the written data into the CGFIFO if it is a write transaction or initiates a G Bus read transaction Such transactions are called CG C790 to G Bus transactions The masters on the G Bus can initiate a single double word operation or a burst operation of up to 8 quad words 16 double words When G Bus masters init...

Page 101: ...nsaction to locate data in the proper word lane Figure 7 3 Bi Endian Support Note that all internal registers except those for the SDRAMC are located on the G Bus See Chapter 4 Address Maps for more information Little Endian Big Endian F E D C B A 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 A B C D E F 7 6 5 4 3 2 1 0 F E D C B A 9 8 3 2 1 0 7 6 5 4 B A 9 8 F E D C 127 0 127 0 0 1 2 3 4 5 6 7 8 9 A B ...

Page 102: ... begins to count down When the counter counts to zero and there is no response from any target a bus error is signaled Since the C790 Bus Clock is twice as fast as the G Bus Clock we can state the following constraint C790 Bus Counter G Bus Counter 2 n where n is the maximum latency of G C transfer This implies that the C790 bus countdown always expires sooner than the G Bus countdown if there is ...

Page 103: ... Undefined GC Upper Internal Register Address 0x80 R 64 0x1E00_0FFF GC Lower Internal Register Address 0x88 R 64 0x1E00_0000 GC Upper MEM Address 0 0x90 R W 64 Undefined GC Lower MEM Address 0 0x98 R W 64 Undefined GC Upper MEM Address 1 0xA0 R W 64 Undefined GC Lower MEM Address 1 0xA8 R W 64 Undefined GC Upper MEM Address 2 0xB0 R W 64 Undefined GC Lower MEM Address 2 0xB8 R W 64 Undefined GC Up...

Page 104: ...n Register Fields Bit s Name Description Type Initial Value 63 1 Reserved Must be written as zeroes and returns zeroes when read Read only 0 0 EN Endianness 1 Big Endian 0 Little Endian Read Pin defined 7 6 2 C790 Bus Control Register The Bus Control Register enables various functions on the C790 Bus The fields of the Bus Control Register are detailed below and in Table 7 3 63 32 0 32 31 7 6 5 4 3...

Page 105: ... 0 C790 Bus Latency Timer Enable 1 Enable 1 5 CGM3E R W CG memory Mapping Window 3 Enable 1 Enable 0 Disable 0 4 CGM2E R W CG memory Mapping Window 2 Enable 1 Enable 0 Disable 0 3 CGM1E R W CG memory Mapping Window 1 Enable 1 Enable 0 Disable 0 2 CGM0E R W CG memory Mapping Window 0 Enable 1 Enable 0 Disable 0 1 ROMWE R O CG ROM Mapping Window Enable 1 Enable 0 Disable 1 0 IOWE R O CG Internal Reg...

Page 106: ...the Bus Status Register are detailed below and in Table 7 4 Note that read errors are detected by the transaction originator 63 32 0 32 31 1 0 0 E R R 31 1 Table 7 4 C790 Bus Status Register Fields Bit s Field R W Description Initial Value 63 1 R O Reserved Must be written as zeroes and returns zeroes when read 0 0 ERR R W C790 Bus Error 1 Bus Error occurred 0 No bus error Error is generated when ...

Page 107: ...8 4 Table 7 5 C790 Bus Bad Address Register Fields Bits Field R W Description Initial Value 63 32 R O Reserved Must be written as zeroes and returns zeroes when read 0 31 4 ERR R O Bad C790 Address Undefined 3 0 R O Reserved 0x0 7 6 5 CG Upper Internal Register Address UIRA The Upper Internal Register Address defines the upper internal register address for devices on the G Bus 63 32 0 32 31 0 UIRA...

Page 108: ...Description Initial Value 63 32 R O Reserved Must be written as zeroes and returns zeroes when read 0 31 0 LIRA R O Lower Internal Register Address 0x1E00_1000 7 6 7 CG Upper ROM Address Register UROMA The Upper ROM Address register defines the upper address for ROM SRAM external I O devices on the G Bus 63 32 0 32 31 0 UROMA 32 Table 7 8 CG Upper ROM Address Register Fields Bits Field R W Descrip...

Page 109: ...tten as zeroes and returns zeroes when read 0 31 0 LROMA R O Lower ROM Address 0x1F00_0000 7 6 9 CG Upper PCI Address Register CGUPA0 CGUPA1 CGUPA2 CGUPA3 The CG Upper PCI Address Register defines the upper address of the CG mapping window CGUPA0 CGUPA1 CGUPA2 CGUPA3 These addresses should be aligned to the last byte of the word boundary 63 32 0 32 31 0 CGUPA 32 Table 7 10 CG Upper PCI Address Reg...

Page 110: ...iption Initial Value 63 32 R O Reserved Must be written as zeroes and returns zeroes when read 0 31 0 CGLPA0 R W Upper Address Undefined 7 6 11 GC Upper Internal Register Address Register GCUIRA The GC Upper Internal Register Address register defines the upper bound register address of the C790 Bus that any G Bus master can access 63 32 0 32 31 0 GCUIRA 32 Table 7 12 GC Upper Internal Register Add...

Page 111: ...n Initial Value 63 32 R O Reserved Must be written as zeroes and returns zeroes when read 0 31 0 GCLIOA R O Lower I O Address 0x1E00_0000 7 6 13 GC Upper Memory Address Register GCUMAx The GC Upper Memory Address Register defines the upper address of the GC memory mapping window These addresses should be aligned to the quad word QW boundary 63 32 0 32 31 0 GCUMA 32 Table 7 14 GC Upper Memory Addre...

Page 112: ...eroes and returns zeroes when read 0 31 0 GCLMA R W GC Lower Memory Address Undefined 7 6 15 Interrupt Status Register IRSTAT The Interrupt Register reports the status of the internal and external interrupt requests An interrupt is generated if a bit in the register is set to 1 and its corresponding mask bit in the Mask register is set to 1 63 32 0 32 31 0 RSTAT 32 Table 7 16 C790 Interrupt Status...

Page 113: ...16 External Interrupt 1 IRMSK 16 0 R W IRSTAT 15 External Interrupt 0 IRMSK 15 0 R W IRSTAT 14 External Interrupt Mac 1 IRMSK 14 0 R W IRSTAT 13 External Interrupt Mac 0 IRMSK 13 0 R W IRSTAT 12 PCI G Bus Bridge 1 IRMSK 12 0 R W IRSTAT 11 SPI IRMSK 11 0 R W IRSTAT 10 UART1 IRMSK 10 0 R W IRSTAT 9 UART0 IRMSK 9 0 R W IRSTAT 8 Timer 2 IRMSK 8 0 R W IRSTAT 7 Timer 1 IRMSK 7 0 R W IRSTAT 6 Timer 0 IRM...

Page 114: ... 7 6 17 C790 Bus Latency Timer LT The latency timer specifies the maximum period in which the slave has to acknowledge the master The counter starts counting down automatically when the master asserts the SYSASTARTB signal The counter is decremented at every C790 bus clock cycle If the counter is down to zero and the slave device does not respond a C790 Bus error is generated and the master genera...

Page 115: ... written as zeroes and returns zeroes when read 0 2 NMI EXT R O External NMI input 1 1 NMI WDOG R O Timer Watchdog at Time2 1 0 NMI ECC R O ECC uncorrectable Error 1 7 6 19 G Bus Master Latency Timer The latency timer specifies the maximum period in which the master can hold the G Bus when other masters are requesting the G Bus The counter is decremented at every G Bus clock cycle When the counter...

Page 116: ...63 8 R O Reserved Must be written as zeroes and returns zeroes when read 0 7 0 GBBMLT R W G Bus Broken Master Latency Timer Is counted down by the G Bus clock 0xFF 7 6 21 G Bus Slave Latency Timer The slave latency timer specifies the maximum period in which the slave must acknowledge the master The counter is decremented at every G Bus clock The counter starts counting down when the master assert...

Page 117: ... assert the G Bus request signal after it receives the Retry signal and releases the G Bus The minimum value is 2 This timer is counted down by the G Bus clock 63 32 0 32 31 8 7 0 0 RTT 24 8 Table 7 24 G Bridge Retry Timer Fields Bits Field R W Description Initial Value 63 8 R O Reserved Must be written as zeroes and returns zeroes when read 0 7 0 RTT R W Retry Timer 0x02 ...

Page 118: ...3 6 R O Reserved Must be written as zeroes and returns zeroes when read 0 5 GCM4E R W GC memory Mapping Window 4 Enable 1 Enable 0 Disable 0 4 GCM3E R W GC memory Mapping Window 3 Enable 1 Enable 0 Disable 0 3 GCM2E R W GC memory Mapping Window 2 Enable 1 Enable 0 Disable 0 2 GCM1E R W GC memory Mapping Window 1 Enable 1 Enable 0 Disable 0 1 GCM0E R W GC memory Mapping Window 0 Enable 1 Enable 0 D...

Page 119: ...ailed below and in Table 7 26 Note that read errors are detected by the transaction originator 63 32 0 32 31 1 0 0 E R R 31 1 Table 7 26 G Bridge Status Register Fields Bit s Field R W Description Initial Value 63 1 R O Reserved Must be written as zeroes and returns zeroes when read 0 0 ERR R W G Bus Error when the G bridge is the G Bus master 1 Bus Error occurred 0 No bus error Error is generated...

Page 120: ... 32 31 0 ERR 32 Table 7 27 C790 Bus Status Register Fields Bits Field R W Description Initial Value 63 32 R O Reserved Must be written as zeroes and returns zeroes when read 0 31 0 ERR R O Bad G Bus Address Undefined 7 6 26 G Bus Arbiter Request Status Register This register indicates which G master is requesting the G Bus 63 32 0 32 31 16 15 0 0 Req 15 0 16 16 Table 7 28 G Bus Arbiter Request Sta...

Page 121: ... 1 PCI G Bus Bridge 0 Req 0 G Bridge 7 6 27 G Bus Arbiter Granted Status Register This register indicates which G Bus master the G Bus is granted to 63 32 0 32 31 16 15 0 0 Grnt 15 0 16 16 Table 7 30 G Bus Arbiter Granted Register Fields Bits Field R W Description Initial Value 63 16 R O Reserved Must be written as zeroes and returns zeroes when read 0 15 0 Grnt 15 0 R O G Bus Granted 0 Granted 1 ...

Page 122: ...rbiter Master Status Register Fields Bits Field R W Description Initial Value 63 16 R O Reserved Must be written as zeroes and returns zeroes when read 0x0000 15 0 Stat 15 0 R O G Bus Master Status 0 Normal 1 Broken 0x0000 7 6 29 G Bus Arbiter Control Register The Control Register enables disables granting the ownership of G Bus to G Bus masters 63 32 0 32 31 16 15 0 0 GEn 15 1 1 16 15 1 Table 7 3...

Page 123: ...iter for five PCI devices 8 1 1 1 General Specifications The G Bus is a Toshiba proprietary on chip bus that has the following important characteristics G Bus operates at up to 66 MHz G Bus has non multiplexed 32 bit addressing and 32 64 bit data transfers G Bus can support multiple masters G Bus has a Retry mechanism to support delayed transactions The PGB is designed with the following features ...

Page 124: ...nsactions for all G Bus master configuration I O and memory write commands to PCI up to eight transactions at a time Implements mapping functions between G Bus and PCI addresses 32 bit G Bus to 32 bit PCI I O mapping No support for the ISA aware mode On chip PCI arbiter for up to five PCI master devices Allows use of external arbiter The PGB is based on a 66MHz PCI core The bridge logic interfaces...

Page 125: ...PCI_REQ_OUT ARB_GNT 4 ARB_REQ 4 app_reset_out pgbgAddr 31 0 pgbgData 63 0 pgbgBEB7 0 pgbgRdB pgbgWrB pgbgAck32B pbgbAck64B pgbgLastB pgbgBStartB pgbgBurstB pgbgRetryB pgbgBSize pgbgReqB pgbgIntB_ sysResetB gbsgBusClk gbsgBusErrB gcbgPGBGntB gcbgPGBRegCSB gbsgRelB gbsgAddr 31 0 gbsgData 63 0 gbsgBEB 7 0 gbsgRdB gbsgWrB gbsgAck32B gbsgAck64B gbsgLastB gbsgBStartB gbsgBurstB gbsgRetryB gbsgBSizeB PCI...

Page 126: ...gnal fed out to GBUS pgbgAddr 31 0 G Bus Address Out pgbgData 63 0 G Bus Data Out pgbgBEB 7 0 G Bus Byte Enables Out pgbgRdB G Bus Read Out pgbgWrB G Bus Write Out pgbgAck32B G Bus 32 bit Ack Out pbgbAck64B G Bus 64 bit Ack Out pgbgLastB G Bus Last signal Out pgbgBStartB G Bus Start Out pgbgBurstB G Bus Burst Out pgbgRetryB G Bus Retry Out pgbgBSize G Bus Quad Word Count Out pgbgReqB G Bus Request...

Page 127: ...a PCI Master initiate reads simultaneously Writes can be posted on the PCI side and reads can be delayed on the G Bus side concurrently The reverse can also occur 8 2 1 G Bus Write to PCI Bridge Master Write To improve performance on the G Bus the following Bridge master write strategy is used Receive write data in the PCI write FIFO if there is enough space to hold the entire data burst Retry the...

Page 128: ...completed in Lt clock cycles then the Wait State Phase is terminated and the next phase the Retry Phase is started The value of Lt is programmable at pgbCSR 23 16 and will be set to a default value of 16 at Reset The PGB causes a G Bus timeout on all PCI errors parity or fatal that happen during this phase To do this the PGB stops responding and causes a timeout bus error on the G_Bus to occur For...

Page 129: ... time An Orphaned Read results if the G Bus Master that initiated the Delayed Read does not return to complete the read The PGB reports orphaned reads by posting an interrupt after a timeout period equal to 216 clocks The PGB causes a G Bus timeout on all PCI errors parity or fatal that happen during this phase To do this the PGB issues a retry to all cycles with any address not equal to the faile...

Page 130: ...e Logic Command Generation And Address Decode Wait State Logic Status Reg Fatal Error Interrupt Logic Parity Error Interrupt Logic Word Count P C I C O R E Retry until matching G Bus cycle detected Return G Bus data Idle Wait timer expires PCI completion PCI completion G Bus Timeout P C I E r r o r G Bus Read Cycle T r a n s f e r c o m p le t e Retry all cycles Wait current cycle O r p h a n e d ...

Page 131: ... O can also be non burst 32 bit or 64 bit single data transactions 8 2 3 1 Posted Write The PGB breaks large PCI bursts of data into smaller bursts that fit into the PCI Bridge write FIFO The PGB write FIFO can hold a burst of size two quad wards The core provides the word count of the current burst to the G Bus Any burst transaction that either comes in with a size not conforming to the sizes of ...

Page 132: ...t returned within 16 clock cycles the core issues a Delayed Read to the PCI Master but continues fetching the data from the G Bus side of the core For both burst and single Memory space transactions the PGB performs G Bus pre fetching until the PCI core indicates last word fetched When the PCI core indicates last word the FIFO is flushed The PGB uses a burst size of four 64 bit words for the specu...

Page 133: ...egister The PCI core supports a subset of the possible PCI transactions Table 8 3 shows the supported PCI transaction types in each direction Table 8 3 Supported PCI transaction types C BE Transaction Type PCI to G Bus G Bus to PCI 0000 Interrupt Acknowledge No Yes 0001 Special Cycle No Yes 0010 I O Read Yes Yes 0011 I O Write Yes Yes 0100 Reserved No Yes 0101 Reserved No Yes 0110 Memory Read Yes ...

Page 134: ...ver the entire system 8 2 7 Lower Address Bits For RAM access the G Bus address bits gbsgAddr 1 0 are always forced to 0 and during RAM burst transactions linear sequential addressing is always performed For RAM transactions PGB ensures that these lower bits are transmitted as 0 in both directions 8 2 8 G Bus to PCI Address Mapping Addition method The PGB performs G Bus to PCI address mapping usin...

Page 135: ...orting errors to the G Bus If a PCI to G Bus write cycle encounters a PCI error the G Bus transfer single or burst is completed with undefined data G Bus errors are not Target Dest Path Target FSM Target Address Path membase 0 membase 1 membase 2 I O base 0 M e m b a s e 0 M e m b a s e 1 I O b a s e 0 PCI Map CORE 4 4 L 36 folding unfolding registers muxes Bus holding Decoder 36 pgbase 0 pgbase 1...

Page 136: ...r are ignored When any of the above PCI errors occur during a G Bus Master read the PGB forces a retry to the current cycle issues a retry to all other cycles and then causes a timeout for the next request to the failed address An attempt by a G Bus Master to cross a g2pWindow boundary is an error condition The PGB posts an interrupt to the G Bus and the PGB goes through the G Bus motion for the t...

Page 137: ...t use the PCI Bus for at least 16 PCI clocks after it is granted the bus it is assumed broken and the Arbiter stops granting it the bus 8 2 11 5 PCI Arbiter Implementation The TX7901 allows both internal and external arbiters In the case of internal arbiters PGB requests are connected to Port0 of the arbiter so there is no need to make a connection to the outside of the chip In contrast it is requ...

Page 138: ... data and parity The Hst bit in the pgbCSR register decides whether the PGB is in the Host Mode or in the Satellite Mode During PCI Reset the application should set this bit to 1 to configure the core to perform Host functions or set this bit to 0 to configure the core to behave as a PCI0 PCI0_ReqB PCIO_GntB Req0 Gnt0 Req1 Gnt1 Req2 Gnt2 Req3 Gnt3 Req4 Gnt4 Arbiter PCI0 Req1 Gnt1 Req2 Gnt2 Req0 Gn...

Page 139: ...this state until RESET is deasserted and a PCI request is received 8 2 12 3 The G Bus Interface At Reset all G Bus PCI interface registers are set to initial conditions Pending interrupt requests are cleared All transactions and operations in progress are cleared Bridge transaction processing is disabled PCI Configuration Space and G Bus register interface cycles remain enabled 8 2 13 Retry reques...

Page 140: ...4 below Details of the PCI configuration bit assignments are given in Section 8 7 The PGB PCI configuration register map is shown in Table 8 4 below Table 8 4 PGB PCI Configuration Register Map 31 16 15 0 R O Device ID R O Vendor ID 102Fh 00h Status Command 04h R O Class Code 000000h R O Revision ID 00h 08h R O Reserved R O Header Type 00h Master Latency Timer 0 Cache line Size 0 0Ch Memory Base A...

Page 141: ...nfiguration access modes are supported based on the hostMode bit in the G Bus control and status register When hostMode is False the Satellite Mode Configuration Register accesses by the CPU are not allowed through the G Bus Configuration read and write accesses by the CPU are not allowed even through PCI Configuration cycles using a g2p window Configuration Register read and write accesses are al...

Page 142: ...shows an address map for PGB Registers Table 8 6 PGB Register Address Map Register Name G Bus Address 0x1E00_4FFF Timer Counter 0x1E00_4000 0x1E00_3FFF Reserved for PGB 0x1E00_31b0 regSwapCtrl 0x1E00_31a8 p2gSwapCtrl 0x1E00_31a0 g2pSwapCtrl 0x1E00_3198 Ia 0x1E00_3190 p2gBase3 0x1E00_3188 p2gBase2 0x1E00_3180 p2gBase1 0x1E00_3178 p2gBase0 0x1E00_3170 g2pCycleType 0x1E00_3168 g2pBase3 0x1E00_3160 g2...

Page 143: ...r R W PCI Error Set when a PCI Parity or Fatal error takes place during a PCI transaction with a G Bus Master PGB interrupt is generated when an error occurs Cleared during reset or by writing a 1 to it 0 9 Wer R W Window Error Set when G Bus Master attempts to cross a g2pWindow Cleared during reset or by writing a 1 to it 0 8 Ger R W G Bus error Set by PGB Master on GBUSERR Cleared during reset o...

Page 144: ...gister pairs are compared to the current G Bus address on each Gbstart cycle For each pair if the G Bus address is greater than or equal to g2pLower and the G Bus address burstSize 1 is less than g2pUpper the address is judged to be within that G2Pwindow and a PCI cycle is initiated When a PCI cycle is initiated g2pLower is subtracted from the G Bus address and g2pBase is added to the remainder to...

Page 145: ...Field R W Description 63 32 R O Reserved 0 31 3 g2pUpper R W Upper boundary of G Bus Address Cleared during reset 0 2 0 R O Reserved 0 8 3 2 2 2 g2pLower Address Registers g2pLower0 g2pLower1 g2pLower2 g2pLower3 The functionality of these registers is described in Section 8 3 2 2 above The fields of these registers are further detailed in the following figure and Table 8 9 63 32 0 32 31 3 2 0 g2pL...

Page 146: ...efine which of the 15 possible PCI cycle types are performed G Bus access to this register is allowed using the G Bus single cycle mode 31 29 28 27 26 24 23 21 20 19 18 16 0 e 3 0 type 3 0 e 2 0 type 2 3 1 1 3 3 1 1 3 15 13 12 11 10 8 7 5 4 3 2 0 0 e 1 0 type 1 0 e 0 0 type 0 3 1 1 3 3 1 1 3 Table 8 11 g2pCycleType Register Field Definitions Bit s Field R W Description 31 29 R O Reserved Read back...

Page 147: ...e corresponding C BE 3 1 It is also important to note however that only a Read is allowed when the type field is set to 3 b110 and a Write would cause a Dual Address Cycle to be initiated The PGB does not support Dual Address Cycles however Furthermore the cache configuration over the entire system should be given careful consideration before using cache coherency commands where the type field is ...

Page 148: ...se provides the base address of the G Bus transaction performed 8 3 2 3 1 p2g Base Address Registers p2gBase When a G Bus cycle is initiated p2gBase is added to the PCI offset address to produce the effective G Bus address G Bus access to these registers is allowed using the G Bus single cycle mode The p2g Base Address Register fields are detailed below and in Table 8 13 63 32 0 32 31 3 2 0 p2gBas...

Page 149: ...8 14 g2pSwapCtrl Register Field Descriptions Bit s Field R W Description 63 16 R O Reserved 0 for Read operations Is ignored by Write operations 15 13 R O Reserved 0 for Read operations Is ignored by Write operations 12 BigW3 R W Window 3 Swapper Default after reset is 1 for Big Endian 0 for Little Endian 1 Swap 0 Straight 11 9 R O Reserved 8 BigW2 R W Window 2 Swapper Default after reset is 1 for...

Page 150: ...ions Bit s Field R W Description 63 16 R O Reserved 0 for Read operations Is ignored by Write operations 15 13 R O Reserved 0 for Read operations Is ignored by Write operations 12 BigW3 R W Window 3 Swapper Default after reset is 1 for Big Endian 0 for Little Endian 1 Swap 0 Straight 11 9 R O Reserved 8 BigW2 R W Window 2 Swapper Default after reset is 1 for Big Endian 0 for Little Endian 1 Swap 0...

Page 151: ...gister is located on the PGB registers The user must input the same value into regSwapH and regSwapL Regardless of whether ByteSwapping is performed or not one of these values is written to the regSwap bit Table 8 16 regSwapCtrl Register Field Descriptions Bit s Field R W Description 63 57 R O Reserved 56 regSwapH R W Same contents as bit 0 Default is 0 if Little Endian ie Big Endian 0 1 if Big En...

Page 152: ...gisters cannot be written to from the G Bus If pgbCSR 2 and pciCommand 2 are both cleared the G Bus master will not be able to initiate PCI master transactions This is why pciCommand 2 is dual ported onto G Bus register pgbCSR 1 By dual porting pciCommand 2 onto G Bus register pgbCSR 1 the PGB can be in the SatelliteMode and a G Bus master can still become the PCI master 8 4 2 p2gBase 3 Dual Porti...

Page 153: ...st Bridge and Satellite core provide the following major features 32 bit PCI bus path 32 or 64 bit G Bus data path PCI 2 1 compliant Master operations and Target operations Eight location FIFO in each data path Full Bandwidth Burst Mode Memory Write and Invalidate support Memory Read Multiple support Dual Address Cycle support Loadable Configuration Space Fast Back to Back Target cycles support Au...

Page 154: ...d data Output Multiplexer Multiplexes addresses and data to the output registers Output Registers Drive the PCI I O buffers with addresses and data PCI ADOUT Register Registers data and addresses from the PCI bus Master Read FIFO Stores data from the PCI bus for Master Read cycles Dual ported 16 x 64b Target Write FIFO Stores data from the PCI bus for Target Write cycles Dual ported 16 x 64b Maste...

Page 155: ...egister Output Multiplexer Multiplexer Register Multiplexer Register DMA Register Master Write FIFO Target Read FIFO Configuration Control Registers PCI Bus Register Command Decode Parity Master Read FIFO Target Write FIFO Address Compare Target State Machine Master State Machine CORE To G Bus Master and Target Interface Blocks I O Block ...

Page 156: ...ENB PCI_IRDY_ENB PCI_PERR_ENB PCI_PAR_ENB PCI_REQ_ENB PCI_RST_INB PCI_CLK_INB PCI_GNT_INB PCI_ADIN PCI_CBEINB PCI_FRAME_INB PCI_IRDY_INB PCI_TRDY_INB PCI_DEVSEL_INB PCI_STOP_INB PCI_PERR_INB PCI_PAR_IN PCI_IDSEL_IN PCI_REQ_OUTB PCI_ADOUT PCI_CBEOUTB PCI_FRAME_OUTB PCI_IRDY_OUTB PCI_TRDY_OUTB PCI_DEVSEL_OUTB PCI_STOP_OUTB PCI_PERR_OUTB PCI_PAR_OUT PCI_SERR_OUTB Output Enables to I O Ports Control a...

Page 157: ...PAR_ENB OUT 1 PCI_PAR_OUTB output enable PCI_PERR_ENB OUT 1 PCI_PERR_OUTB output enable PCI_REQ_ENB OUT 1 PCI_REQ_OUTB output enable Table 8 19 Control and Data From I O Pads to Core Listed Alphabetically Signal Dir Width Description PCI_ADIN IN 32 Address Data PCI_CBEINB IN 4 Command Byte Enable PCI_CLK_IN IN 1 PCI Clock PCI_DEVSEL_INB IN 1 Device Select PCI_GNT_INB IN 1 Bus Grant PCI_FRAME_INB I...

Page 158: ... which the PCI Target device retries beyond the retry count To prevent this the core provides the programmable RETRY_TIMEOUT register whose value sets the number of retries that the core will perform as a Master before abandoning a cycle This register is at configuration address 0x41 The default value for the register is 0x80 which is well in excess of the PCI 2 1 requirement for new devices A wri...

Page 159: ...6 are used at this address Access Read Only Table 8 22 Configuration PCI Device ID Register Bit s Description Reset PGB0 0x0040 15 0 Device ID PGB1 0x0041 8 7 3 PCI Command Register Address 04h Bits Used Bits 15 0 are used at this address Access Read Write Table 8 23 Configuration PCI Command Register Bit s Description Reset 15 10 Reserved 0x0 9 Fast Back to Back Master Enable 0 8 System Error Ena...

Page 160: ...ort Status Set when the core initiates a PCI transaction and is terminated by the Target 0 Status 11 Signaled Target Abort Status 0 Status 10 9 Device Select Timing Indicates timing of PCI_DEVSEL when the core responds to a PCI transaction as a Target 01 R O 8 Data Parity Detected 0 Status 7 Fast Back to Back Capable Status Flag 1 R O 6 RESERVED 0 R O 5 66 MHz Capable Status Flag 1 Status 4 0 Rese...

Page 161: ...ne Size Register Address 0Ch Bits Used Bits 7 0 are used at this address Access Read Write For better performance use values up to 32 20h If this register is 00h then Memory Write and Invalidate commands will be converted into Memory Write commands Also Memory Read Line and Memory Read Multiple commands will be converted into Memory Read commands Refer to sections 3 1 1 3 1 2 and 6 2 4 of the PCI ...

Page 162: ...egister sets the minimum number of PCI clock cycles that the core will be guaranteed access to the PCI bus After this count has expired the core will surrender the PCI bus as soon as the Arbiter grants the bus to other PCI Master devices 00h 1 0 Reserved Hardwired to 0 0h 8 7 9 Header Type Address 0Ch Bits Used Bits 23 16 are used at this address Access Read Write Header Type is defined in Section...

Page 163: ...s Used Bits 7 0 are used at this address Access Read Write Interrupts are not implemented so Writes to this register should not be performed The Interrupt Line is defined in section 6 2 4 of the PCI 2 1 Specifications Table 8 32 Interrupt Line Register Bits Description Reset 7 0 Interrupt Line Routing 00h 8 7 13 Interrupt Pin Register Address 3Ch Bits Used Bits 15 8 are used at this address Access...

Page 164: ...0h 8 7 15 MAX_LAT Register Address 3Ch Bits Used Bits 31 24 are used at this address Access Read Write Table 8 35 MAX_LAT Register Bits Description Reset 7 0 Sets value of MAX_LAT See PCI 2 1 Specifications Section 6 2 4 for details Is in units of 0 25 µS 00h 8 7 16 TRDY Timeout Value Address 40h Bits Used Bits 7 0 are used at this address Access Read Write Table 8 36 Configuration TRDY Timeout Va...

Page 165: ...30T Nov 2001 8 43 8 7 17 Retry Timeout Value Address 40h Bits Used Bits 15 8 are used at this address Access Read Write Table 8 37 Configuration Retry Timeout Value Bits Description Reset 7 0 Sets number of retries that the core will perform as Master 80h ...

Page 166: ... the DMAC features in the TX7901 Eight independent channels of direct memory access DMA Chaining via link lists of records Fixed round robin priority arbitration 128 bit C790 bus support capable of transferring 1 6 2 1 GB second Burst transfer of 1 to 8 quad words on the C790 bus Bi endian support on the C790 bus 64 bit G Bus support capable of transferring 400 533 MB second 32 64 bit I O device s...

Page 167: ...eme is used When fixed priority is programmed the DMA channel priority corresponds to the FPL 3 0 field in the CCR registers FPL 3 0 0000 is the highest priority whereas FPL 3 0 1111 is the lowest priority If two DMA channels have the same priority level the DMA channel number determines the priority The DMA channel with the lower channel number is assigned the higher priority For example if chann...

Page 168: ...rements the address after each access 9 1 3 Block Transfers In the block mode each hardware or software DMA request sends a request to the DMAC to transfer a block of data The size of the block of data in bytes is in the current byte count register BCR0 BCR7 When a block mode DMA channel is granted access the actual transfer takes place in two steps 1 The DMAC arbitrates for the source bus transfe...

Page 169: ... FIFO The DMAC now arbitrates for the destination bus and when the bus is granted it transfers the slice of data from the FIFO to the destination device Once the slice of data is transferred the DMAC is ready to serve other DMA channels Essentially in the slice mode the entire DMA transfer is broken down into a number of slice transfers At the end of the very last slice transfer the DMAC generates...

Page 170: ...s on the C790 bus for this scenario The completion interrupt is generated after Slice 2 DMA Bus Cycle 2 finishes DMA Bus Cycle 1 C790 Bus Cycle DMA Bus Cycle 3 DMA Bus Cycle 1 DMA Bus Cycle 2 DMA Bus Cycle 2 C790 Bus Cycle SLICE 1 SLICE 2 Figure 9 3 C790 Bus Operations With Cycle Stealing When DMA channel 5 is active and cycle stealing is disabled the C790 can use itself only between the slice tra...

Page 171: ...in memory and writes into the corresponding control registers in the DMAC Then the DMAC tries to fetch the data from the source memory pointed to by the source address register and puts it into the destination memory pointed to by the destination address register After completion of the data transfer the DMAC fetches the subsequent Descriptor if the Next Record Pointer does not contain the NULL va...

Page 172: ...C finishes with a single C790 bus Single operation Figure 9 5 is an example of the cycle division in little endian memory In this example the memory transfer is divided into a Single cycle a Burst cycle of 2 quad words two burst cycles of 8 quad words and then two single cycles 000000000 Hex FFFFFFFF0 Hex 8 QW Boundary 8 QW Boundary 8 QW Boundary 1QW Unaligned Address Cycle Division 000000000 Hex ...

Page 173: ...s Next Record Pointer 0X2000 0x1000 0x1004 0x1008 0x100C Byte Count Source Address Destination Address Next Record Pointer 0X4000 0x2000 0x2004 0x2008 0x200C Byte Count Source Address Destination Address Null Pointer 0X0 0x4000 0x4010 0x4020 0x4030 Transfer 1 Transfer n Figure 9 6 DMAC Operation 9 1 11 Restarting a Disabled Channel Text Later 9 1 12 Reprogramming an Active Channel Text Later 9 1 1...

Page 174: ...1140 BCR1 Channel 1 Byte Count Register 0x1E00_1150 NRPR1 Channel 1 Next Record Pointer Register 0x1E00_1160 0x1E00_11F0 RESERVED 0x1E00_1200 CCR2 Channel 2 Control Register 0x1E00_1210 CSR2 Channel 2 Status Register 0x1E00_1220 SAR2 Channel 2 Source Address Register 0x1E00_1230 DAR2 Channel 2 Destination Address Register 0x1E00_1240 BCR2 Channel 2 Byte Count Register 0x1E00_1250 NRPR2 Channel 2 N...

Page 175: ...0x1E00_1660 0x1E00_16F0 RESERVED 0x1E00_1700 CCR7 Channel 7 Control Register 0x1E00_1710 CSR7 Channel 7 Status Register 0x1E00_1720 SAR7 Channel 7 Source Address Register 0x1E00_1730 DAR7 Channel 7 Destination Address Register 0x1E00_1740 BCR7 Channel 7 Byte Count Register 0x1E00_1750 NRPR7 Channel 7 Next Record Pointer Register 0x1E00_1760 0x1E00_17F0 RESERVED 0x1E00_1800 GCSR Global Control and ...

Page 176: ...access at the same time and are at the same priority level DMA Channel 1 will be granted access 0000 Level 0 0001 Level 1 0010 Level 2 0011 Level 3 0100 Level 4 0101 Level 5 0110 Level 6 0111 Level 7 1000 Level 8 1001 Level 9 1010 Level 10 1011 Level 11 1100 Level 12 1101 Level 13 1110 Level 14 1111 Level 15 18 CCS R W 0 C790 Cycle Stealing 0 Setting this bit enables the DMAC to allow the C790 to ...

Page 177: ... is set it enables G Bus error interrupts 0 Disable G Bus error interrupts 1 Enable G Bus error interrupts 8 R O 0 Reserved 0 7 SDL R W 0 Source Device Location 0 This bit indicates whether the source device is located on the C790 bus or the G Bus 0 Source device is on the C790 bus 1 Source device is on the G Bus 6 R O 0 Reserved 0 5 4 SCM R W 00 Source Device Counting Mode 00 These bits indicate ...

Page 178: ...ading this bit means the following 0 No normal completion interrupt 1 Normal completion interrupt pending When writing this bit means the following 0 The interrupt bit is cleared 1 The interrupt bit is ignored 2 CCI R W 0 Chain Mode Completion Interrupt When reading this bit means the following 0 No chain mode completion interrupt 1 Chain completion interrupt pending When writing this bit means th...

Page 179: ... bit means the following 0 The interrupt bit is cleared 1 The interrupt bit is ignored 9 2 3 Source Address Registers SAR0 SAR7 These eight registers contain the source addresses of the DMA operation in progress for each of the eight DMA channels 63 32 0 32 31 0 SA 31 0 32 Table 9 5 Source Address Register Field Definitions Bit s Field R W Default Description 63 32 R O 0 Reserved 31 0 SA R W 0 Sou...

Page 180: ...ammed in the Chain Mode CHN 1 the destination address is loaded from the address pointed to by the Next Record Pointer Register when a whole block of data has been completely transferred 9 2 5 Byte Count Register BCR0 BCR7 These eight registers contain the byte counts of the DMA operation in progress for each of the eight DMA Channels 63 32 0 32 31 24 23 0 0 BC 23 0 8 24 Table 9 7 Current Byte Cou...

Page 181: ...ved 31 0 NRP R W 0 Next Record Pointer Points to the next record A Null value indicates the end of the list 9 2 7 Global Control and Status Register GCSR This register controls the global behavior of the DMAC 63 32 0 32 31 30 29 28 27 26 24 23 22 1 0 G I N T G N C I G C C I G C B I G G B I 0 G I N T E 0 F R P 1 1 1 1 1 3 1 22 1 Table 9 9 Global Control and Status Register Field Descriptions Bit s ...

Page 182: ...n some DMA channels 26 24 R O 0 Reserved 23 GINTE R W 0 DMA Global Interrupt Enable 0 Disable All DMAC Interrupts 1 Enable All DMAC Interrupts 22 1 R O 0 Reserved 0 FRP R W 0 Fixed Round robin Priority 0 Fixed 1 Round robin 9 2 8 C790 Bus Error Address Register CBEADDR Table 9 10 lists the fields of the C790 Bus Error Address Register 63 32 0 32 31 0 CBEA 31 0 32 Table 9 10 C790 Bus Error Address ...

Page 183: ...rror Address Register Table 9 11 G Bus Error Address Register Field Descriptions Bit s Field R W Default Description 63 32 R O 0 Reserved 31 0 GBEA R O 0 G Bus Error Address When the DMAC is the master on the G Bus and encounters a bus error the first bus error address is recorded in this register Further bus error addresses are ignored until the G Bus error interrupt GBI is cleared ...

Page 184: ...the counter The external clock input can be configured to trigger the counter on its rising or falling edge 10 1 2 Pulse Generator Mode In this mode the Timer output can be configured to provide waveforms of specific frequency and duty ratio 10 1 3 Watchdog Timer Mode In this mode the timer monitors and times out system runaway conditions 10 1 4 Internal or External Clock Division The internal or ...

Page 185: ...h as Timer 2 The internal connections within Timer 0 and Timer 1 are similar to Timer 2 except for each of them lacking some features present in Timer 2 Figure 10 1 Timer Module Connections inside the TX7901 TX7901 G Bus I F Signal Internal Clock Interrupt 6 tmrglnt0B Interrupt 7 tmrglnt1B Interrupt 8 tmrglnt2B Internal Reset NMI Timer 0 Interval Timer Mode only Timer 1 Interval Timer Mode and Pul...

Page 186: ...ivider 1 2 to 1 256 Register r w Control Logic Timer Control Register Interrupt Control Register Interval Mode Register Pulse Gen Mode Register Watchdog Mode Register Clock Source Select Periodic Interval Timer Output Pulse Generator Output Watchdog Timer Output b16 tmrgInt2B tmrpg2B demux CLEAR Control Logic G Bus TX7901 TIMIN1 TIMIN2 TX7901 Internal Clock Interrupt 6 Interrupt 7 Interrupt 8 TIMO...

Page 187: ... registers if this value is 0xF0 Otherwise it generates a dummy Acknowledge signal to terminate the cycle This was implemented to accommodate the G Bus specifications sysResetB I System Reset input signal from the TX7901 to the Timer This Active Low signal when asserted resets all three timer units simultaneously tgdisB I Disable Signal input from the TX7901 to the Timer This Active Low signal whe...

Page 188: ...se train generated from this output are programmable by writing appropriate values to the respective timer s configuration registers tmrwdtreq2B O Active Low output of Timer 2 when configured as a Watchdog Timer This output is demultiplexed onto either the NMI input or the Master Reset input of the TX7901 and the demultiplexer is controlled by bit 16 of the Watchdog Mode Register tmrgdata 63 0 O D...

Page 189: ...nter Reset When Stopped Enable R W When the Counter is stopped by clearing the TCE bit to 0 this bit determines whether the Counter should also be reset at that time 0 0 Holds the count value i e does not clear it when the counter is stopped by the TCE bit 1 Clears the count value when the counter is stopped by the TCE bit 4 R O Reserved 3 ECES External Clock Trigger Edge Select R W Selects the cl...

Page 190: ...R W Description 31 16 R O Reserved 15 TIIE Timer s Interval Timer Interrupt Enable R W Sets up interrupt enable disable in the interval timer mode 0 0 Disable mask 1 Enable 14 1 R O Reserved 0 TZCE Interval Timer Zero Clear Enable R W Determines whether to clear the counter to 0 after the count value matches compare register A If not cleared the counter is halted at that value If the timer interru...

Page 191: ...3 3 Table 10 6 Field Descriptions for Divider Registers TMCCDR0 TMCCDR1 TMCCDR2 Bit s Field Field Name R W Description 31 3 R O Reserved 2 0 CCD Counter Clock Divide value R W Specifies the divisor value of the selected clock The value used is 2 raised to the power n 1 when a binary value n is used in this field 000 000 2 001 4 010 8 011 16 100 32 101 64 110 128 111 256 Note The register fields ma...

Page 192: ...rrupt Enable R W Timer Pulse Generator Interrupt by TMCPRB Enable sets up enable disable for the timer interrupt that occurs in the Pulse Generator Mode when the TMCPRB and the counter value match 0 0 Disable mask 1 Enable 14 TPIAE TMCPRA Interrupt Enable R W Timer Pulse Generator Interrupt by TMCPRA Enable sets up enable disable for the timer interrupt that occurs in the Pulse Generator Mode when...

Page 193: ...aster Reset The default value is 0 15 TWIE Watchdog Timer Interrupt Enable R W Sets interrupt enable disable in the Watchdog Timer Mode 0 0 Disable mask 1 Enable 14 8 R O Reserved 7 WDIS Watchdog Timer Disable R W Disables the Watchdog Timer Mode when WDIS is set to 1 and then sets the TCE bit of the timer control register to 0 0 Note The WDIS bit will automatically be cleared to 0 after the watch...

Page 194: ... has no effect functionally 2 TPIBS Timer Pulse Generator B TMCPRB interrupt status 1 2 R W When the Timer Pulse Generator interrupt is enabled by setting the TPIBE bit and the counter value matches the compare register TMCPRB value during counting the TPIBS bit is set asserting the TMINTREQ line Low By clearing the TPIBS bit the TMINTREQ line is de asserted High clearing the interrupt request 0 0...

Page 195: ...the counter value matches the compare register TMCPRA value during counting the TIIS bit is set asserting the TMINTREQ line Low By clearing the TIIS bit the TMINTREQ line is de asserted High resetting the interrupt request 0 0 read No interrupt request is being generated 1 read Counter has matched compare register A and an interrupt request is being generated for the Interval Timer 0 written Reset...

Page 196: ...mpare Register B 31 24 23 16 0 TCVB 8 8 15 0 TCVB 16 Table 10 10 Field Descriptions for Time Compare Registers TMCPRAx TMCPRBx Compare Register Field Field Name R W Description TCVA 23 0 Timer Compare Value A 23 0 R W Contains the 24 bit compare value A for the timer Used in all modes 0xFFFFFF TCVB 23 0 Timer Compare Value B 23 0 R W Contains the 24 bit compare value B for the timer Used in the Pu...

Page 197: ...ister TMTCR to 0b00 binary The Counter Clock Select CCS bit of the TMTCR register determines whether the internal system clock or the external clock input is selected Dividing down the selected internal or external clock by the value set up for the divisor generates the actual clock frequency This value is set up in the Counter Clock Divide CCD field of the divider register TMCCDR and is activated...

Page 198: ...ing restarts asserting the interrupt request signal when the count value reaches the value in TMCPRA When the TZCE bit is 0 counter operation is stopped when the count matches the value of TMCPRA This is summarized in the table below Table 10 12 Interrupt control with the TIIE and TZCE bits TIIE TZCE Action or inaction when counter has reached the set up value 0 X Timer Interval Interrupt Requests...

Page 199: ... TIIE 1 0 1 TMINTREQ Count Value Counter reset enabled Counter disabled Counter halted but not reset Zero clear disabled Zero clear enabled Counter Enabled Counter reset disabled TMCPRA Compare Value 0x000000 changes Time TIIS 0 written TIIS 0 written TIIS 0 written Timer interrupt disabled Timer interrupt enabled Count Value TMCPRA Compare Value 0x000000 TMODE 00 TCE 1 CRE 0 CCS 1 TCZE 1 TIIE 1 E...

Page 200: ...666 667 8 0b010 8 33 MHz 120 ns 2 01 138 889 8 333 333 16 0b011 4 17 MHz 240 ns 4 03 69 444 4 166 667 32 0b100 2 08 MHz 480 ns 8 05 34 722 2 083 333 64 0b101 1 04 MHz 960 ns 16 11 17 361 1 041 667 128 0b110 520 83 kHz 1 92 us 32 21 8 681 520 833 256 0b111 260 42 kHz 3 84 us 64 42 4 340 260 417 50 0 MHz Decimal CCDR CCD Freq Unit Resolution Unit 24bit Max Time s Generate 60Hz interval Counter value...

Page 201: ... TPIAS in the Timer Interrupt Status Register TMTISR is set to 1 The interrupt control logic asserts TMINTREQ when the TPIAS bit is set and also enabled by having the TPIAE bit of the TMPGMR register set as well If the TPIAE bit is cleared it masks the TPIAS bit from being forwarded as an interrupt request and masks assertion of TMINTREQ Low Similarly the interrupt control logic asserts TMINTREQ w...

Page 202: ...er Contents TX7901 User s Manual Rev 6 30T Nov 2001 10 19 Figure 10 5 Pulse Generator Mode Operation Count Value TMCPRB Compare Value TMCPRA Compare Value 0x000000 TMODE 01 CCS 0 FFI 1 TIIE 0 TCE 1 CRE 0 TMFFOUT TCE 0 TCE 1 Time ...

Page 203: ...the 24 bit counter the Watchdog Timer Clear TWC bit of the Watchdog Timer Mode Register TMWTMR is set to 1 The TWC bit is automatically reset to 0 after the 24 bit counter is cleared When the Timer Counter Enable bit TCE is cleared and the Watchdog Timer Disable WDIS bit of the TMWTMR register is set to 1 the Watchdog Timer Counter is disabled However when the WDIS bit is 0 count operation cannot ...

Page 204: ...usly cleared to 0 assuming in this example that bit TZCE of the Interval Timer Mode Register TMITMR is set Figure 10 7 Interval Timing Example Using Internal Clock The above figure illustrates a case in which Timer Compare Value A TCVA is 3 and the counter is triggered by the external clock input The Timer s Interval Timer Interrupt Status bit TIIS of the Interrupt Status Register TMTISR is set at...

Page 205: ...taneously with TMPGMR being written to Figure 10 9 Pulse Generator Mode Timing Example 10 5 4 2 Watchdog Timer Mode Interrupt Timing Figure 10 10 illustrates the use of the Watchdog Timer This mode is the same as the Internal Timer Mode except that the Watchdog Timer issues an NMI or Master Reset instead of an interrupt Figure 10 10 Watchdog Timer Timing Example 0 0 0 0 0 0 1 1 1 1 1 2 2 2 2 2 3 3...

Page 206: ...tains an interrupt status register to identify up to 16 different interrupt sources There is a corresponding 16 bit interrupt mask register When the corresponding mask bit is cleared the interrupt request is disabled Once an interrupt request is detected and its corresponding mask bit is set an interrupt request is asserted to the C790 Table 11 1 lists all the maskable interrupt sources Table 11 1...

Page 207: ...s associated with the interrupt controller are the Interrupt Status Register and the Interrupt Mask Register Table 11 2 Interrupt Controller Registers Address Field Register Name 1E00_20E0 IRSTAT Interrupt Status Register 1E00_20E8 IRMASK Interrupt Mask Register 11 3 1 Interrupt Status Register IRSTAT The Interrupt Status Register is periodically updated with the state asserted or unasserted of ea...

Page 208: ...s to be selectively masked from causing an interrupt to the C790 The following figure and Table 11 4 detail the fields of the Interrupt Mask Register 31 16 IRMASK 31 16 16 15 0 IRMASK 15 0 16 Table 11 4 Interrupt Mask Register Field Description Bits Field R W Description 31 0 IRMASK R W Interrupt Mask 0 Mask the interrupt request 1 Enable the interrupt request ...

Page 209: ...ection CSMA CD protocol In the full duplex mode the controller implements the IEEE 802 3x MAC Control Layer and the PAUSE Operation for flow control On the host side it supports direct connection to the 64 bit G Bus The MAC can be either a G Bus master or slave device An internal DMA controller manages the transfer of data blocks between memory and the MAC s internal FIFOs relieving the C790 of ma...

Page 210: ...nsfer transmit frame data from memory to the Transmit FIFO TxFIFO 4 Transfer received frame data from the Receive FIFO RxFIFO to memory The priority for each task depends on whether the RxFIFO is close to being full or the TxFIFO is close to empty The software can also select the priority The DMA provides logic for controlling the G Bus master read and write operations The functions controlled inc...

Page 211: ...d packet from the MII and stores it in the RxFIFO The receive block has circuits for checking the CRC value and packet lengths It also has an address table for accepting or rejecting of a packet based on its destination address The TxFIFO and RxFIFO are both 1 KB in size Controls for the following network operations are included in the MAC Controls to enable and disable transmit and receive circui...

Page 212: ...ceive Data Valid When asserted indicates that the PHY is presenting recovered and decoded nibbles on macxRxD 3 0 Remains asserted continuously from the first nibble through the final nibble of the frame Synchronous with the rising edge of macxRxClk macxRxD 3 0 Input Receive Nibble Data Synchronous with the rising edge of macxRxClk macxRxEr Input Receive Error When asserted for one or more macxRxCl...

Page 213: ...Register Width R W Description Notes 0x000 63 0 R Reserved 1 2 0x008 CCReg 63 0 R W Command Configuration Register 1 0x010 TFCReg 63 0 R W Transmit Frame Configuration 1 0x018 RFCReg 63 0 R W Receive Frame Configuration 1 0x020 TSReg 63 0 R Transmit Status Register 1 0x028 RSReg 63 0 R Receive Status Register 1 0x030 TIMReg 63 0 R W Transmit Interrupt Mask Register 1 0x038 TIReg 63 0 R Transmit In...

Page 214: ...AC Pause Frames Transmitted 1 0x258 LFTCnt 63 0 R W Long Frames Transmitted 1 0x260 TCCnt 63 0 R W Total Collisions 1 0x268 LCCnt 63 0 R W Late Collision 1 0x270 MCCnt 63 0 R W Multiple Collision 1 0x278 SCCnt 63 0 R W Single Collision 1 0x280 EDCnt 63 0 R W Excessive Deferrals 1 0x288 TRECnt 63 0 R W Transmit Retry Errors 1 0x290 TUECnt 63 0 R W Transmit Underflow Errors 1 0x298 63 0 R W Reserved...

Page 215: ...ress E 4 0x678 63 0 R W Physical Address F 4 Notes 1 In the tables above registers must be accessed as 64 bit registers even when their widths are smaller For such registers the remaining bits are Reserved are ignored when written to and are read back as zeroes 2 All registers that are marked as Reserved are ignored when written to and are read back as ones 3 The contents of Internal Test Register...

Page 216: ...of reset this register s default value is 0x0080_0160 31 30 28 27 26 25 24 23 22 16 Diag Mode 0 NBO 0 MDCSel 0 1 3 1 2 2 7 15 13 12 8 7 5 4 3 2 1 0 0 DSL 4 0 PBL BAR Cnt Rst Rx Rst Tx Rst Sw Rst 3 5 3 1 1 1 1 1 Table 12 7 CCReg Register Field Descriptions Bit s Field R W Description 31 DiagMode R W When set the MAC is in the diagnostic mode all FIFO units are accessible to the C790 and all counter...

Page 217: ...it is self clearing 0 0 SwRst RW Software Reset Reset is immediate and it is equivalent to resetting the counters the transmitters the receivers and the MII management block It does not affect registers including interrupt status or diagnostic registers This bit is self clearing 0 Note The Busy bit in the MII control register must be 0 before this bit is set 12 3 1 2 Transmit Frame Configuration R...

Page 218: ... 10 TxEnCRC R W Transmit CRC Enable 0 While CRC is low the CRC check sum is neither calculated nor appended to each transmitted frame 9 TxEnPad R W Pad Transmit Data 0 While this bit is set the MAC will automatically append data to a frame less than 60 bytes in length The TxEnCRC bit should be set also so a valid CRC is appended to the frame Otherwise the frame will be transmitted with a bad CRC I...

Page 219: ...l poll the Descriptor first and then transmit frames When cleared it will stop the transmission If this bit is cleared during the transmission of a frame the frame is completely transmitted before stopping This bit is self clearing when transmission is stopped error occurred and TxEnhalt is set or suspended Descriptor is not available To resume the transmission process the driver should set this b...

Page 220: ...tering of multicast frames and perfect address filtering of physical frames 00 MAC performs perfect address filtering of all incoming frames according to the perfect table 23 16 RxSOFTh 7 0 R W Receive Start of Frame Threshold 0000_1000 This threshold indicates how many 8 byte units of a frame must be received in the RxFIFO before the first DMA request If the frame size is less than RxSOFTh the tr...

Page 221: ...e MAC enters a running reception state It will poll the Descriptor first then transfer the incoming frame data to memory When cleared this bit will stop reception If this bit is cleared during the reception of a frame the frame is completely received before the port is stopped This bit is self clearing when the reception is stopped error occurred To resume the transmission process the driver shoul...

Page 222: ...Running waiting for end of transmission 110 Running waiting for end of transmission and next Descriptor is not available 111 Reserved 27 15 R O Reserved 0x000 0 14 13 TxFrmType R W Transmit Frame Type 00 00 Ethernet RFC 894 encapsulation 01 IEEE802 2 RFC 1042 encapsulation 10 VLAN I 11 VLAN II 12 TxExDefer R W Excessive Deferral 0 When set indicates that the transmission was aborted because of an ...

Page 223: ...be acquired by the MAC Transmission process is suspended 1 TxPStop R W Transmit Process Stopped 0 When set indicates that the transmission process has been suspended 0 TxGood R W Good Frame 0 When set indicates that a frame transmission was completed without error This bit will be set regardless of the state of SQE TxSCol TxMCol and TxDefer This bit will not be set in the case that TxLCol TxExDefe...

Page 224: ...hen set indicates that frame truncation caused by a frame that does not fit within the current Descriptor buffers occurred and that the MAC does not own the next Descriptor The frame is truncated 13 RxPStop R O Receive Process Stopped 0 When set indicates that the reception process was suspended 12 RxNoBuf R O Receive Buffer Unavailable 0 When set indicates that the next Descriptor in the receptio...

Page 225: ...driven when a bit is set to 1 in the Transmit Interrupt Register Upon the completion of reset this register defaults to 0x0000_0000 31 26 25 24 23 22 21 20 19 18 17 16 0 TxFB ErrM Tx Stop M Tx Good M Tx LCol M TxEx DefM TxEx Col M TxF Undf M TxC Undf M TxC RtyM ExC Def MTx 6 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXCM ColM TxCS ColM TxC L Col M TxC ColM TxC Long M TxC Pause M Tx...

Page 226: ...letion of reset this register s value is 0x0000_0000 31 26 25 24 23 22 21 20 19 18 17 16 0 TxFB Err Tx Stop Tx Good Tx LCol TxEx Def TxEx Col TxF Undf TxC Undf TxC Rty ExC Def 6 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXCL Col TxCM Col TxCS Col TxC Col TxC Long TxC Pause TxC Gt1K TxC 1K TxC 511 TxC 255 TxC 127 TxC 64 TxC BC TxC MC TxC Frm TxC Byte 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ...

Page 227: ... 24 23 22 21 20 19 18 17 16 0 RxFB ErrM Rx Stop M Rx Read FrmM Rx Buf ErrM RxF Overf M RxC NoFi FM RxC No DesM RxC JabM ExC Frag M 7 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RxC Unds M RxC NoAln M RxC CRC M RxC ErrM RxC Long M RxC Pause M RxC Gt1K M RxC 1KM RxC 511M RxC 255M RxC 127M RxC 64M RxC BCM RxC MCM RxC FrmM RxC Byte M 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 12 15 RIMReg Regis...

Page 228: ...RxC CRC RxC Err RxC Long RxC Pause RxC Gt1K RxC 1K RxC 511 RxC 255 RxC 127 RxC 64 RxC BC RxC MC RxC Frm RxC Byte 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 12 16 RIReg Register Field Descriptions Bit s Field R W Description 31 25 R O Reserved 0x00 24 RxFBErr R W Receive Fatal Bus Error 0 23 RxStop R W Reception Stopped or Suspended 0 22 RxReadFrm R W Received a Readable Frame 0 21 RxBufErr R W Truncate...

Page 229: ...two Station Address registers named the Station Address I and II Registers For the MAC Station Address SA5 SA4 SA3 SA2 SA1 SA0 the registers should be written as follows 31 24 23 16 SA3 SA2 8 8 15 8 7 0 SA1 SA0 8 8 Station Address I 31 16 0 16 15 8 7 0 SA5 SA4 8 8 Station Address II Table 12 17 Station Address I Register Field Descriptions Bits Field R W Description 31 24 SA3 R W MAC Station Addre...

Page 230: ... has been captured 0 12 3 1 12 Transmit Pause Frame Timer Register TPFTReg The Transmit Pause Frame Timer Register is used by the MAC control sub layer when the MAC is configured for full duplex operation and flow control is requested by the host or an RxFIFO underflow The contents of this register are included in the MAC control frame as the n slots variable where n slots represents the number of...

Page 231: ...R W Two Level VLAN tag ID 0x0000 15 11 VLANI 15 0 R W One Level VLAN tag ID 0x0000 12 3 1 14 Transmit Frame Descriptor Pointer Register TDPReg The Transmit Descriptor Pointer Register contains the address of the first Descriptor of the frame to be transmitted The system must set this register to a properly initialized frame Descriptor before it enables transmission A valid address must be aligned ...

Page 232: ...lt value is 0x0000_0000 31 16 RxNextID 31 16 16 15 4 3 0 RxNextID 15 4 0 12 4 Table 12 23 RDPReg Register Field Descriptions Bits Field R W Description 31 4 RxNextD R O First Receive Descriptor Address 31 4 0x0000 3 0 R O Reserved 12 3 1 16 Current Descriptor Pointer Register CDPReg The Current Descriptor Pointer Register contains the address of the last Frame Descriptor which the MAC DMA accessed...

Page 233: ...d Descriptions Bit s Field R W Description 31 4 CurrentD R W Descriptor Address 31 4 0x0000 3 0 R O Reserved 0000 12 3 1 18 Receive frame Current Descriptor Pointer Register RCDReg The Receive frame Current Descriptor Pointer Register contains the address of the current Descriptor used for reception When the MAC Rx is stopped of is suspended i e RFCReg RxStart 0 this register shows the Descriptor ...

Page 234: ...fined as 0 96 microseconds In 10 Mb Ethernet the IPG is defined as 9 6 microseconds The IPG Time IPGT is used to space back to back transmit packets The transmit state machine has an intrinsic delay of 6 clock cycles macxTxClk between packets In other words with IPGT set to 0 the resultant IPG will be 6 clock cycles Thus the equation is IPG 6 IPGT T where T is the period of macxTxClk Here is a sim...

Page 235: ... 1 7 Table 12 29 NBTBReg Register Field Descriptions Bit s Field R W Description 63 15 R O Reserved 0 14 8 IPGR1 R W Non Back To Back IPG part 1 0x00 7 R O Reserved 0 6 0 IPGR2 R W Non Back To Back IPG part 2 0x12 The IPGT is used to space non back to back transmit packets The equation is IPG 6 IPGR1 IGPR2 T where T is the period of macxTxClk Following is a simple chart of IPGT values for 100 Mb a...

Page 236: ...ccurs 12 3 2 2 Total Good Frame Transmitted This counter does not count those frames that are transmitted with errors i e collision fragments partial frames due to FIFO underflow and frame transmissions that are aborted due to excessive deferral excessive collisions or late collisions 12 3 2 3 Multicast Frames Transmitted This counter counts the good multicast frames that are transmitted 12 3 2 4 ...

Page 237: ...l legal collisions 12 3 2 14 Late Collision This 32 bit counter counts the number of late collisions 12 3 2 15 Single Collision This 32 bit counter counts the number of times a frame is transmitted successfully with one collision This count does not include frames that are transmitted with errors or collisions that are forced during half duplex flow control 12 3 2 16 Multiple Collision This 32 bit...

Page 238: ...ude the broadcast frames 12 3 2 23 Broadcast Frames Received This 32 bit counter counts the broadcast frames received successfully 12 3 2 24 Frames Received RxFrame64 This 32 bit counter counts the frames received successfully that are 64 bytes in length including CRC 12 3 2 25 Frames Received RxFrame127 This 32 bit counter counts the frames received successfully that are between 65 and 127 bytes ...

Page 239: ...unts the received frames with an incorrect CRC that are aligned on an 8 bit boundary The frames must be greater than 63 bytes and less than or equal to the maximum size bytes If the RXER signal is asserted by the PHY during the reception of a frame this counter will be incremented in addition to the Receive Error Counter 12 3 2 34 Misaligned Frames Received This 32 bit counter counts the received ...

Page 240: ... 12 3 2 38 No RxFIFO Missed Frames This 32 bit counter counts the frames that are not able to be stored in the RxFIFO which has overflowed 12 3 2 39 No RxDescriptor Missed Frames This 32 bit counter counts the frames that are not able to be stored in the RxFIFO since there is no receive Descriptor ...

Page 241: ...i te Bu sy 16 5 5 4 1 1 Figure 12 3 Fields of MIIM Control Register Table 12 31 MIIM Control Register Field Descriptions Bit s Field Description 15 11 PA 4 0 PHY Address The 5 bit address of the PHY being read or written 10 6 REG 4 0 Register Address The 5 bit address of the MIIM register being read or written 5 2 Reserved 1 Write MIIM Write When set indicates that this is a write operation on the...

Page 242: ... Register Field Descriptions Bit s Field Description 15 0 Pdata 15 0 PHY Data The 16 bit data read from the PHY after an MIIM read The 16 bit data to be written to the PHY before an MIIM write This register should not be written to if the Busy bit in the MIIM Control Register is 1 12 3 4 Address Filtering The MAC supports 48 bit addresses in two separate address tables the Perfect Table and the Ha...

Page 243: ...t is used for address filtering 62 48 Reserved 47 0 PA Physical Address PA5 PA4 PA3 PA2 PA1 PA0 63 62 48 47 40 39 32 31 24 23 16 15 8 7 0 V 0 PA5 PA4 PA3 PA2 PA1 PA0 1 15 8 8 8 8 8 8 12 3 4 2 Hash Table The Hash Table process is used in individual and group hash filtering It stores 512 bits that serve as hash bucket heads and one physical 48 bit MAC address This process can be used in two differen...

Page 244: ...a Access Controller TX7901 User s Manual Rev 6 30T Nov 2001 12 36 12 3 5 FIFO Addresses The FIFO address space is for debugging purposes It allows the C790 to read or write to the FIFO This may be done only in the FIFO diagnostic mode ...

Page 245: ...e There are two Descriptor lists one for receive and one for transmit The base address of each list is written to two registers the Transmit Descriptor Pointer Register and the Receive Descriptor Pointer Register The Descriptor lists reside in C790 memory Each Descriptor can point to a maximum of two buffers A data buffer consists of either an entire frame or part of a frame but it cannot exceed o...

Page 246: ...the size in bytes of the first data buffer If this field is zero the MAC ignores this buffer and only uses buffer 2 The buffer size should be a multiple of 8 If it is not the least three bits are ignored 47 37 Buffer2 Size Indicates the size in bytes of the second data buffer If RxChain is set Address Chained the MAC ignores this buffer and fetches the next Descriptor 36 RxERing Receive End of Rin...

Page 247: ...RC is invalid and the byte count is greater than or equal to 64 bytes 8 RxCRCErr CRC Error When set indicates that the frame received is greater than or equal to 64 bytes and has a correct CRC 7 RxUnds Undersized Frame When set indicates that the frame received is less than 64 bytes and has a correct CRC 6 RxFrag Fragment When set indicates that the frame received is less than 64 bytes and has an ...

Page 248: ...le race condition between the MAC fetching a Descriptor and the driver setting an ownership bit 62 59 Must be set to 0 58 48 Buffer1 Size 2K Indicates the size in bytes of the first data buffer If this field is 0 the MAC ignores the buffer and uses buffer2 47 37 Buffer2 Size 2K Indicates the size in bytes of the second data buffer If TxChain is set Address Chained the MAC ignores this buffer and f...

Page 249: ...orted due to a collision occurring later than 512 bit times 6 TxLCar Loss of Carrier When set indicates the CRS input is Low during the transmission of a frame 5 SQE Signal Quality Error Missed When set indicates that the SQE test on the macxCOL signal line is not detected at the end of a transmission 4 TxUndf Transmit Underflow When set indicates that the TxFIFO had an underflow condition during ...

Page 250: ...or to close a Descriptor 2 RxFrmReq This is used for DMA to transfer data to memory from a RxFIFO 12 5 1 2 Transmit In the running state the transmit process polls the transmit Descriptor list for frames requiring transmission After polling starts it continues in either the sequential Descriptor ring order or in the chained order When frame transmission is complete status information is written in...

Page 251: ...he MAC does not automatically poll the transmit Descriptor list the driver must issue a transmit poll demand command after rectifying the cause of the suspension 12 5 1 2 3 Transmit Frame DMA request The TxFIFO uses a two signal handshake for request and acknowledge synchronization The first signal TxFrmReq is active when the TxFIFO is capable of having data written to it The amount of data is a c...

Page 252: ...d by the reception frame threshold RxSOFTh This RxSOFTh is set in the RFCReg Receive Frame Configuration Register and determines the minimum frame required in the RxFIFO to initiate the DMA operation Once this threshold is met the entire frame needs to be read out of the RxFIFO regardless of any error conditions and bits set in the RFCReg If the MAC detects any errors before the threshold is met t...

Page 253: ...w in the TxFIFO In general TxSOFTh should be more than 64 bytes multiple of PBL and meet TxSOFTh PBL TxFIFO TxFIFO PBL PBL RxSOFTh and PBL are used to monitor the RxFIFO operation RxSOFTh specifies when the first DMA request is asserted after a frame is received PBL is used to warn the MAC that only this number of free spaces is left in the RxFIFO For each frame after reaching RxSOFTh subsequent D...

Page 254: ...smission The TxFIFO does not overwrite the first 64 bytes of a frame until they are transmitted successfully In the event of a collision the FIFO pointers are reset to the beginning of the frame These bytes are retransmitted after a collision back off period has elapsed 12 5 2 3 2 Half Duplex Flow Control While in the half duplex mode the host system can have the transmitter force a collision by a...

Page 255: ...FO is capable of holding multiple frames Frame boundaries in the FIFO are recognized by the SOF and EOF If there is no SOF before EOF the data are ignored 12 5 2 4 RxFIFO Specific Functions The RxFIFO buffers frames as they are received from the network 12 5 2 4 1 Multiple Frames The RxFIFO has the ability to hold multiple frames at any given time If several short frames are received before the MA...

Page 256: ...filtered if RxSOFTh is set to 64 bytes or more 12 5 2 4 6 Error Conditions Error conditions can be found in the Frame Interrupt Register 12 5 2 4 7 Overflow When the RxFIFO overflows the interrupt bit RFIFO is set The receiver will ignore all subsequent data from that frame If the flow control enable bit RxFCEn is set the MAC will send out a flow control frame while configured for full duplex It w...

Page 257: ...ss When this register is written MAC will initiate the read by diving MDC with a valid clock and MDIO with the proper preamble start code and data from the MII control register The Busy bit in the MII control register is set for the duration of the operation Data read from the PHY are stored in the MII data register and are available for the host to read when the Busy bit is zero Writing to an MII...

Page 258: ...ware reset 2 Counter reset 3 Transmit reset 4 Receive reset The transmit and receive reset bits reset the transmit and receive FIFO as well as the other logic associated with the data path These resets do not have any effect on the counter values although during transmission or reception reset the associated counters are not updated The counter reset will reset the event counters only The software...

Page 259: ...Chapter 13 Removed TX7901 User s Manual Rev 6 30T Nov 2001 13 1 13 Removed ...

Page 260: ...Chapter 13 Removed TX7901 User s Manual Rev 6 30T Nov 2001 13 2 ...

Page 261: ...d lengths from five to eight bits an optional parity bit and one or two stop bits If enabled the parity can be odd even or forced to a defined state Interrupts can be generated from any of ten sources Figure 14 1 UART Block Diagram Note If RCLK_BAUD is tied high RCLK is connected to BAUD if RCLK_BAUD is tied low RCLK is taken from an external Receive clock fed in through the RCLK pin If an externa...

Page 262: ...he UART has been designed so that most internal operations are synchronized by the gbsBusClk signal This results in minor timing differences between the UART and the original device which means that the core is not clock for clock identical with the original device 14 2 Functional Description 14 2 1 Transmit Operation Transmission is initiated by writing the data to be sent to the TX Holding Regis...

Page 263: ...trol lines RTS DTR OUT1 and OUT2 can be set or cleared by writing to the Modem Control Register The current status of the input Modem Control Lines DCD RI DSR and CTS can be read from the Modem Status Register Bit 2 of this register will be set if the NRI line has changed from Low to High since the register was last read If enabled an interrupt will be generated when any of the DSR CTS RI or DCD s...

Page 264: ...utput Data Terminal Ready MSR 0 control bit Active Low DMAC Interface urtgRxRdyB Output DMA Handshake Goes Low when RX FIFO contains data urtgTxRdyB Output DMA Handshake Goes Low when TX FIFO is empty G Bus Bridge Interface urtgIntB Output Interrupt Request Goes Low whenever one of the enabled interrupts becomes valid This signal goes to the interrupt controller inside the G Bus Bridge Note Active...

Page 265: ...Write Only 2 There are no RXFIFO or TXFIFO registers 3 The base address for UART0 is 0x1E00_7000 The base address for UART1 is 0x1E00_8000 Table 14 3 Device Register Addressing for UARTs 0 1 Big Endian Mode G Bus Register Offset Address 7 2 Byte Enables D L A B Bank Offset Acronym Name Notes 00 0000_00 0111 0 0 RBR Receive Buffer Register R O See 14 4 2 00 0000_00 0111 0 0 THR Transmit Holding Reg...

Page 266: ... is enabled 14 4 4 Line Control Registers LCR0 LCR1 Table 14 4 lists the fields of the Line Control Registers This register specifies line control parameters and contains the DLAB bit which makes the Divisor Latch addresses accessible Table 14 4 Line Control Register Field Descriptions Bit Read Write Comments 0 WLS0 Word Length Select 1 WLS1 Word Length Select 2 STB Number of Stop Bits 3 PEN Parit...

Page 267: ...tted nor checked 14 4 4 4 EPS Even Parity Select When EPS 1 and PEN 1 an even number of ones is sent and checked When EPS 0 and PEN 1 an odd number of ones is sent and checked 14 4 4 5 SP Stick Parity When set 1 the Parity bit is forced into a defined state dependent upon the values of EPS and PEN If EPS 1 PEN 1 the Parity bit is transmitted and checked as 0 If EPS 0 PEN 1 the Parity bit is transm...

Page 268: ...G Bus reading the RX Buffer or by reading all of the FIFO bytes This bit is also cleared whenever the FIFO enable bit is changed 14 4 5 2 OE Overrun Error If the FIFOs are disabled this bit is set if the RX Buffer was not read by the G Bus before new data from the RX Shift Register overwrote the previous contents OE is cleared when the G Bus reads this register If the FIFOs are enabled an overrun ...

Page 269: ... SIN goes into the marking state and it receives the next valid start bit 14 4 5 6 THRE TX Holding Register Empty If the FIFOs are disabled this bit is set to 1 whenever the TX Holding Register is empty and ready to accept new data and it is cleared when the data are transferred to the TX Shift Register If the FIFOs are enabled this bit is set to 1 whenever the TX FIFO is empty and it is cleared w...

Page 270: ...bytes in the RX FIFO and resets its counter logic The RX Shift Register is not affected This bit is self clearing 14 4 6 3 CLRT Clear Transmit FIFO Writing a 1 to this bit clears all the bytes in the TX FIFO and resets its counter logic The TX Shift Register is not affected This bit is self clearing 14 4 6 4 DMA1 DMA Mode 1 This bit determines the DMA mode which the TXRDY and RXRDY pins support On...

Page 271: ... fields of these registers Table 14 9 Fields of Interrupt Identification Registers Bit s Read Comment 6 7 FIFOE Returns 1 if FIFOs enabled otherwise 0 4 5 0 Always returns 0 3 ID2 Interrupt ID Bit 2 Returns 0 if FIFOs disabled 2 ID1 Interrupt ID Bit 1 1 ID0 Interrupt ID Bit 0 0 NINT No interrupt pending Table 14 10 Interpretation of the fields of the Interrupt Identification Registers ID2 ID1 ID0 ...

Page 272: ...ad from the RX FIFO The Timeout timer is restarted on receipt of a new byte from the RX Shift Register or on a G Bus read from the RX FIFO 14 4 7 2 TX FIFO Interrupt The TX Holding Register Interrupt occurs when the TX FIFO is empty It is cleared by writing to the TX Holding Register or by reading from the IIR The TX FIFO Empty interrupt will be delayed one character period minus the last stop bit...

Page 273: ...ty 0 ERBFI Enable RX Buffer Register When set 1 an interrupt is generated if the RX Buffer contains data Note After reset bits 0 through 7 are all 0 14 4 9 Modem Control Registers MCR0 MCR1 Table 14 12 Modem Control Register Fields Bit s Write Read Comment 7 5 X 0 4 Loop Loop Loop back mode 3 OUT2 OUT2 Control Signal 2 OUT1 OUT1 Control Signal 1 RTS RTS Control Signal 0 DTR DTR Control Signal Afte...

Page 274: ...rry Detect 2 TERI Trailing Edge Ring Indicator 1 DDSR Delta Data Set Ready 0 DCTS Delta Clear to Send Note Reading the Modem Status Register clears the Delta bits 14 4 10 1 DCD Data Carry Detect When Loop 0 this is the complement of the DCD input signal When Loop 1 this is equal to the OUT2 bit in the Modem Control Register 14 4 10 2 RI Ring Indicator When Loop 0 this is the complement of the RI i...

Page 275: ...r was last read 14 4 10 9 MSR RESET and SAMPLE TIMING After reset bits D0 through D3 are 0 and can be written to and bits D4 through D7 are inputs A modem status interrupt can be cleared by writing 0 or set by writing 1 to this register A change in any of the modem status input signal levels will be sampled twice by gbsBusClk before there is any change to the Modem Status Register value 14 4 11 Sc...

Page 276: ...ks RefClk MHz G Bus Clock MHz Divide Value Prescaler Output MHz 133 66 6 8 8 333 100 50 0 6 8 333 66 33 3 4 8 333 Table 14 15 Clock Frequency and Percent Error Pre scaled Clock 8 3333 MHz Baud Rate Divisor for 16x clock Error 50 10417 0 00320 75 6944 0 00640 110 4735 0 00320 135 3872 0 00947 150 3472 0 00640 300 1736 0 00640 600 868 0 00640 1200 434 0 00640 1800 289 0 12175 2000 260 0 16026 2400 2...

Page 277: ...e original device this interrupt is reset on the falling edge of WR Transmit register In the UART it is reset on the rising edge of this signal 14 5 3 FIFO Reset Timing When using bits 0 3 of the FIFO Control Register to reset the FIFOs the following timing restrictions apply FCR0 Both FIFOs are reset by the master reset MR and are held unless FCR0 is set to 1 FCR1 The RX FIFO clear requires at le...

Page 278: ...6 1 Package pins For UART1 only SIN and SOUT arrive at the package pins Other input signals are tied internally and other output signals remain open Inputs Level Outputs Remaining Open RCLK L BAUD RCLK_BAUD H OUT1 DCD L OUT2 RI L RTS DSR L DTR CTS L Note that all signals arrive at the package pins for UART0 ...

Page 279: ...face SPI communication unit which accesses serial ROM serial RTC etc The Boot Memory sequencer for Word access BM W is a G Bus interface which accepts G Bus word access and translates the word transaction into byte access to the SPI devices Table 15 1 SPI Register Addresses for TSEI Address Register 0x1E00_9000 GPIO_outreg 0x1E00_9004 GPIO_inreg 0x1E00_9008 GPIO_outenab 0x1E00_900C Reserved 0x1E00...

Page 280: ... divisor Otherwise this program will no longer be able to run on boot ROM Boot address Area General Purpose I O Registers SPI Registers Area 0x1FC0_0000 0x1FC1_0000 Map to Serial EEPROM 0x1e00_9000 0x1e00_A000 TSEI s data direction data status and control registers SPI Memory Map TSEI registers GPIO registers and Boot address area SECR SESR SEDR DDCR GPIO_outreg GPIO_inreg GPIO_outenab Reserved 0x...

Page 281: ...sfer Complete flag SESR SEF 6 SEE 1 Boot mode TSEI system is on 0 1 Normal mode TSEI system is off TSEI system is on 5 BOS 0 Boot mode MSB bit of the SEDR register data7 will be transmitted first compatible to Atmel AT25256 SPI Serial EEPROM 0 1 Normal mode Same as Boot mode LSB bit of the SEDR register data0 will be transmitted first 4 MSTR 1 Boot mode TSEI is configured as master generate clock ...

Page 282: ...ata7 Data6 Data5 Data4 Data3 Data2 Data1 Data0 2 b10 R W R W R W R W R W R W R W R W Access 0 0 0 0 0 0 0 0 Reset When the TSEI system is configured as a master transfers are started by a software write to the SEDR reg Data Direction Register DDCR 7 6 5 4 3 2 1 0 TSS_n TSCLK MOSI MISO 2 b11 R W R W R W R W Access 0 0 0 0 0 0 0 0 Reset 1 1 1 x Boot 1 1 1 x Normal bit Name val Mode Description 5 TSS...

Page 283: ...ad Word 128 bit 16 Byte C790 Bus Width instruction fetch 4 QW 512 bit 64 Byte C790 cache line size cache refill 8 QW 1024 bit 128 Byte G Bus maximum burst size When a read transaction in this address range is on the G Bus BM W initializes TSEI to the Boot configuration see Figure 15 2 First BM W drives CE0 SPI_Port0B to Low the BM W issues a read command 0x03 to serial ROM via TSEI Then 2 Bytes of...

Page 284: ... in out clk cs External SPI Devices Flash memory 0x1E00_9008 in out clk cs SPI Companion Chip FPGA COMIT G Bridge 0 7 port0_in port1_in port2_in port3_in port4_in port5_in GPIO_inreg port0_en port1_en port2_en port3_en port4_en port5_en 0 7 GPIO_outenab 0 7 port0_ou port1_out port2_out port3_out port4_out port5_out GPIO_outreg 0x1E00_9000 0x1E00_9004 Registers Memory Mapped Address SPI External In...

Page 285: ...on detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress A multiple master mode fault detector automatically disables TSEI output drivers if more than one MCU simultaneously attempts to become bus master Pin Control Unit Shift Register Bit Order MUX Read Buffer TSEI Control Unit Clock Control Unit TSEI Control Register TSEI Status Reg...

Page 286: ... a master device to communicate with peripheral slaves having different requirements 15 4 2 TSEI Data and Clock Timing The adjustable data clock timings of the TSEI module are compatible with SPI standard data clock timings The SPI interface allows connection with almost any synchronous serial peripheral device Please see Figure 8 1 and Chapter 8 for a detailed description of the transfer format 1...

Page 287: ...fer If the SS_n pin of a slave is inactive high the device ignores TSCLK clocks and keeps the SDMISO output pin in the high impedance state On a master device the SS_n pin serves as an error detection input for the TSEI If the SS_n pin goes low while the TSEI is a master it indicates that some other device on the TSEI bus is attempting to be a master This attempt causes the master device sensing t...

Page 288: ...STC signal is delayed until SS_n goes High 15 6 2 CPHA EQUALS 1 FORMAT Figure 15 4 shows the transfer format for a CPHA 1 transfer 1 2 3 4 5 6 7 8 Cycle SCK CPOL 0 SCK CPOL 1 MOSI MISO SEF Compatibility Mode TSRC Toshiba Mode TSTC Toshiba Mode SS Master Mode Slave Mode Figure 15 4 CPHA Equals 1 Transfer Format In this transfer format the first bit is shifted in on the second clock edge This will b...

Page 289: ...a is prepared during the next clock cycle Here the RD_n signal is also asserted enabling the output on the data bus AD 7 0 The correct time to sample the value from the data bus is on the next positive clock edge of the CPU clock At the next positive clock edge the RD_n signal is deasserting tri stating the output drivers for the data bus CS_n is deasserted on the following clock edge 15 7 2 Write...

Page 290: ...ag is obsolete in the Toshiba mode Only the Interrupt Controller registers are used to enable or disable interrupts SEE TSEI System Enable 0 TSEI system is off It is necessary to disable the TSEI system to switch between the Toshiba operating mode and the compatibility mode 1 TSEI system is on BOS Bit Order Select This bit determines the data bit which will be transmitted first 0 The MSB bit of th...

Page 291: ...Mode R R R R R W R W Toshiba Mode R C R C R C R C R C R W R W Reset 0 0 0 0 0 0 0 0 SEF TSEI Transfer Complete Flag Compatibility Mode This flag is automatically set to 1 at the end of a TSEI transfer SEF is automatically cleared by reading the SESR register with the SEF bit set Toshiba Mode Switching to the Toshiba Mode clears this flag This flag always reads as 0 and writes to this flag have no ...

Page 292: ... SS_n signal goes to active low while the TSEI is configured as a master MSTR 1 In this case 1 The SEI output pin drivers are disabled and the output pins are placed in the high impedance state 2 The MSTR bit in the SECR register is cleared 3 The SEE bit is forcibly cleared to disable the SEI system 4 An interrupt is generated if the SEIE bit is set The MODF flag is automatically cleared by readin...

Page 293: ...hift Mode 1 Enables the Automated Shift Mode In this Mode a read access to the TSEI data register SEDR will perform the following functions The TSEI data register will be cleared to 00h after it has been read A new transfer will be initiated thus in the Master Mode 8 low bits will be shifted out and 8 new bits will be shifted in The automated shift mode also works when it is combined with a MicroD...

Page 294: ...nput regardless of the value of the DDCR register When TSEI is enabled as a master the function of the TSS_n pin depends on the value of DDCR bit 5 0 The TSS_n pin is used as an input to detect mode fault errors A low TSS_n pin indicates that some other device in a multiple master environment is acting as a master and is trying to select this device as a slave To prevent harmful contention between...

Page 295: ...O line TSEI systems that tie TSDMOSI and TSDMISO together to form a single bi directional data line also need to selectively disable the TSDMISO output When the TSEI system is enabled as a master the TSDMISO pin acts as the master serial data input regardless of the state of this bit 15 9 TSEI System Errors TSEI is only used in the Slave Mode and therefore does not report any errors 15 10 Interrup...

Page 296: ... used to trigger a MicroDMA that reads the data from the TSEI register The other interrupt can be used to trigger a MicroDMA that writes a new value to the data register thus initiating a new transfer TSEI Interrupt Channel 0 TSIC0 Interrupt on MODF or WCOL 1 or SOVF 2 TSEI Interrupt Channel 1 TSIC1 Interrupt on TSRC TSEI Interrupt Channel 2 TSIC2 Interrupt on TSTC The SEIE bit is obsolete in the ...

Page 297: ...s asserted after a completed transfer On the transition of this flag from 0 to 1 an IRQ signal is caused on TSIC0 This will be a pulse that is one clock cycle in length After this a mode fault causes a transition of the MODF flag from 0 to 1 This will not cause another IRQ pulse since SEF is already asserted When SEF is cleared and MODF is still asserted a second IRQ pulse is generated on the MODF...

Page 298: ...ks Clock Description CPU Clock Basic clock supplied to the C790 core data and instruction caches and MMUs System Bus Clock Supplied to the C790 bus and all the devices attached to it SDRAMC G bridge and DMAC G bus Clock Supplied to all IPs PCI MAC UARTS SPI and Timer connected to the G bus The TX7901 clock system provides many different clocking options for all on chip and external devices The Pha...

Page 299: ...v 6 30T Nov 2001 16 2 16 2 Features The main features of the TX7901 clocks are as follows f 2 f 3 f 4 dividers are available for the CPU SysBus clocks Fixed f 2 divider for sysBus gbusClock PLL and divider bypass for scan and memory test modes ...

Page 300: ...4 Bit G Bus Bridge C790 SPI PCIC SDRAM MEMORY Controller DMAC PCI CLK 0 66 MHz CPU Clock System Bus Clock G bus Clock I 32K D 32K BIU IFU LSU DEBUG PCU IU FPU DIV UART x2 BAUDO 50 Hz 256 KHz RCLK DIV MAC x2 RXCLK TXCLK 2 5 10 25 MHz 2 2 Timer Counter x2 TIMIN 0 33 25 MHz 2 DIV DIV Figure 16 1 TX7901 Clock Domain Diagram ...

Page 301: ...igure 16 2 TX7901 Clock Distribution Diagram PLL 2 1 MUX f 2 f 3 f 4 4 1 MUX f 2 2 1 MUX DivSel div1 f x f x CpuClk RefClk PllSel 1 0 DivSel 1 0 SysClk IP Block 2 1 MUX 2 1 MUX extIPclk IPclk IFclk GbusClk SDRAM DIMMS PLL Feedback PLL SyncExt PLL SyncIn 1 0 PLL SyncOut 0 1 0 1 0 1 ...

Page 302: ...mode must not be used as a normal operating mode Its only valid use is for low frequency silicon debugging The PLL also functions as a multiplier to the cpuClk sysClk ratios in addition to de skewing the SDRAMC clock and the external SDRAM clock During normal operation refClk is always in sync with sysClk so that the external SDRAM and TX7901 SDRAM controller are running at the same system bus fre...

Page 303: ...scillator The external oscillator will generate a reference clock to a PHY device The PHY then constructs a very accurate 2 5 MHz 10 MHz 25 MHz TX clock which drives the TX7901 MAC module The FIFO structure inside the MAC module synchronizes data transfer between the MAC clock and G Bus Clock domain 16 4 2 UART Clock The UART module has a Transmit and a Receive clock domain The Receive clock is an...

Page 304: ...Hz 1 562 kHz 781 kHz 195 kHz 16 4 4 PCI Clock The PCI module may operate in either the 33 MHz or 66 MHz mode When the PCI module operates in the 33 MHz mode it will support PCI input clocks from 0 MHz to 33 MHz When it operates in the 66 MHz mode it will support PCI input clocks from 33 MHz to 66 MHz The PCI module uses an externally generated clock The PCI module uses FIFO structures to synchroni...

Page 305: ...pt from ether MAC PHY1 INT_0B I External Interrupt Request 0 INT_1B I External Interrupt Request 1 INT_2B I External Interrupt Request 2 INT_3B I External Interrupt Request 3 INT_4B I External Interrupt Request 4 Clock Interface PLL_DIV0 PLL_DIV1 I To set up divide Ratio between CPU clock to internal System Bus Clock 00 Divide By 1 Test only 01 Divide by 2 10 Divide by 3 11 Divide by 4 PLL_TestOut...

Page 306: ...ontrol Modem Control register 3 status bit UA0_OUT1B O General Control Modem Control register 2 status bit UA0_RTSB O Request to Send Modem Control register 1 status bit UA0_DTRB O Data Terminal Ready Modem Control register 0 status bit UART1 Interface UA1_SIN I Serial Input Data are clocked in using internal RCLK UA1_SOUT O Serial Output Data are clocked out using the output from Baud Rate Genera...

Page 307: ...Target is requesting Initiator to stop the current transaction PCI0_DEVSELB I O Device select it indicates that the current driving device has decoded its address as the target of the current access PCI0_CLK I PCI Clock Input PCI0_PERRB I O Data Parity Error Reporting parity error on all transactions except Special Cycle command PCI0_IDSEL I Initialization Device Select It is used as a chip select...

Page 308: ...bus PCI1_SERRB O System Error Reporting errors for all the address parity errors and data parity error on Special Cycle commands and may optionally be used on any other non parity or system errors PCI1_GNTB I PCI1 Grant PCI1_REQB O PCI1 Request PCI1_GNT0B I PCI1 bus Grant 0B PCI1_GNT1B_PCI0_GNT3B O PCI1 bus Grant 1B Multiplex with PCI0 bus Request 3B PCI1_GNT2B_PCI0_GNT4B O PCI1 bus Grant 2B Multi...

Page 309: ...TX7901 User s Manual Rev 6 30T Nov 2001 17 5 TBD 17 1 JTAG Boundary Scan external test chain configuration Please contact Toshiba to request a BSDL file based on IEEE1149 1b This file contains the required information ...

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